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1; RUN: llc -mattr=addsubiw < %s -mtriple=avr | FileCheck %s2 3define i8 @add8_reg_reg(i8 %a, i8 %b) {4; CHECK-LABEL: add8_reg_reg:5; CHECK: add r24, r226 %result = add i8 %a, %b7 ret i8 %result8}9 10define i8 @add8_reg_imm(i8 %a) {11; CHECK-LABEL: add8_reg_imm:12; CHECK: subi r24, -513 %result = add i8 %a, 514 ret i8 %result15}16 17define i8 @add8_reg_increment(i8 %a) {18; CHECK-LABEL: add8_reg_increment:19; CHECK: inc r2420 %result = add i8 %a, 121 ret i8 %result22}23 24 25define i16 @add16_reg_reg(i16 %a, i16 %b) {26; CHECK-LABEL: add16_reg_reg:27; CHECK: add r24, r2228; CHECK: adc r25, r2329 %result = add i16 %a, %b30 ret i16 %result31}32 33define i16 @add16_reg_imm(i16 %a) {34; CHECK-LABEL: add16_reg_imm:35; CHECK: adiw r24, 6336 %result = add i16 %a, 6337 ret i16 %result38}39 40define i16 @add16_reg_imm_subi(i16 %a) {41; CHECK-LABEL: add16_reg_imm_subi:42; CHECK: subi r24, 13343; CHECK: sbci r25, 25544 %result = add i16 %a, 12345 ret i16 %result46}47 48define i16 @add16_reg_reg_zext(i16 %a, i1 zeroext %b) {49; CHECK-LABEL: add16_reg_reg_zext:50; CHECK: mov r18, r2251; CHECK: clr r1952; CHECK: add r24, r1853; CHECK: adc r25, r1954 %zext = zext i1 %b to i1655 %result = add i16 %a, %zext56 ret i16 %result57}58 59define i32 @add32_reg_reg(i32 %a, i32 %b) {60; CHECK-LABEL: add32_reg_reg:61; CHECK: add r22, r1862; CHECK: adc r23, r1963; CHECK: adc r24, r2064; CHECK: adc r25, r2165 %result = add i32 %a, %b66 ret i32 %result67}68 69define i32 @add32_reg_imm(i32 %a) {70; CHECK-LABEL: add32_reg_imm:71; CHECK: subi r22, 25172; CHECK: sbci r23, 25573; CHECK: sbci r24, 25574; CHECK: sbci r25, 25575 %result = add i32 %a, 576 ret i32 %result77}78 79define i32 @add32_reg_reg_zext(i32 %a, i1 zeroext %b) {80; CHECK-LABEL: add32_reg_reg_zext:81; CHECK: mov r18, r2082; CHECK: clr r1983; CHECK: ldi r20, 084; CHECK: ldi r21, 085; CHECK: add r22, r1886; CHECK: adc r23, r1987; CHECK: adc r24, r2088; CHECK: adc r25, r2189 %zext = zext i1 %b to i3290 %result = add i32 %a, %zext91 ret i32 %result92}93 94define i64 @add64_reg_reg(i64 %a, i64 %b) {95; CHECK-LABEL: add64_reg_reg:96; CHECK: add r18, r1097; CHECK: adc r20, r1298; CHECK: adc r21, r1399; CHECK: adc r22, r14100; CHECK: adc r23, r15101; CHECK: adc r24, r16102; CHECK: adc r25, r17103 %result = add i64 %a, %b104 ret i64 %result105}106 107define i64 @add64_reg_imm(i64 %a) {108; CHECK-LABEL: add64_reg_imm:109; CHECK: subi r18, 251110; CHECK: sbci r19, 255111; CHECK: sbci r20, 255112; CHECK: sbci r21, 255113; CHECK: sbci r22, 255114; CHECK: sbci r23, 255115; CHECK: sbci r24, 255116; CHECK: sbci r25, 255117 %result = add i64 %a, 5118 ret i64 %result119}120 121define i64 @add64_reg_reg_zext(i64 %a, i1 zeroext %b) {122; CHECK-LABEL: add64_reg_reg_zext:123; CHECK: mov r30, r16124; CHECK: clr r31125; CHECK: ldi r26, 0126; CHECK: ldi r27, 0127; CHECK: add r18, r30128; CHECK: adc r19, r31129; CHECK: adc r20, r26130; CHECK: adc r21, r27131; CHECK: adc r22, r26132; CHECK: adc r23, r27133; CHECK: adc r24, r26134; CHECK: adc r25, r27135 %zext = zext i1 %b to i64136 %result = add i64 %a, %zext137 ret i64 %result138}139