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1; RUN: llc < %s -mtriple=avr | FileCheck %s2 3define i8 @and8_reg_reg(i8 %a, i8 %b) {4; CHECK-LABEL: and8_reg_reg:5; CHECK: and r24, r226 %result = and i8 %a, %b7 ret i8 %result8}9 10define i8 @and8_reg_imm(i8 %a) {11; CHECK-LABEL: and8_reg_imm:12; CHECK: andi r24, 513 %result = and i8 %a, 514 ret i8 %result15}16 17define i16 @and16_reg_reg(i16 %a, i16 %b) {18; CHECK-LABEL: and16_reg_reg:19; CHECK: and r24, r2220; CHECK: and r25, r2321 %result = and i16 %a, %b22 ret i16 %result23}24 25define i16 @and16_reg_imm(i16 %a) {26; CHECK-LABEL: and16_reg_imm:27; CHECK: andi r24, 21028; CHECK: andi r25, 429 %result = and i16 %a, 123430 ret i16 %result31}32 33define i32 @and32_reg_reg(i32 %a, i32 %b) {34; CHECK-LABEL: and32_reg_reg:35; CHECK: and r22, r1836; CHECK: and r23, r1937; CHECK: and r24, r2038; CHECK: and r25, r2139 %result = and i32 %a, %b40 ret i32 %result41}42 43define i32 @and32_reg_imm(i32 %a) {44; CHECK-LABEL: and32_reg_imm:45; CHECK: andi r22, 2146; CHECK: andi r23, 20547; CHECK: andi r24, 9148; CHECK: andi r25, 749 %result = and i32 %a, 12345678950 ret i32 %result51}52 53define i64 @and64_reg_reg(i64 %a, i64 %b) {54; CHECK-LABEL: and64_reg_reg:55; CHECK: and r18, r1056; CHECK: and r19, r1157; CHECK: and r20, r1258; CHECK: and r21, r1359; CHECK: and r22, r1460; CHECK: and r23, r1561; CHECK: and r24, r1662; CHECK: and r25, r1763 %result = and i64 %a, %b64 ret i64 %result65}66 67define i64 @and64_reg_imm(i64 %a) {68; CHECK-LABEL: and64_reg_imm:69; CHECK: andi r18, 25370; Per PR 31345, we optimize away ANDI Rd, 0xff71; CHECK-NOT: andi r19, 25572; CHECK: andi r20, 15573; CHECK: andi r21, 8874; CHECK: andi r22, 7675; CHECK: andi r23, 7376; CHECK: andi r24, 3177; CHECK: andi r25, 24278 %result = and i64 %a, 1744674407370955161379 ret i64 %result80}81 82