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1; RUN: llc < %s -mtriple=avr | FileCheck %s2 3; At one point, the 16-vit atomic load/store operations we defined in TableGen4; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW instructions.5;6; This would sometimes cause codegen to fail because LDDW requires 'PTRDISPREGS', and7; so if we attempted to generate an atomic operation on the X register, it would hit8; an assertion;9 10%AtomicI16 = type { %UnsafeCell, [0 x i8] }11%UnsafeCell = type { i16, [0 x i8] }12 13; CHECK-LABEL: foo14define i8 @foo(ptr) {15start:16 17; We should not be generating atomics that use the X register, they will fail when emitting MC.18; CHECK-NOT: X19 %1 = getelementptr inbounds %AtomicI16, ptr %0, i16 0, i32 0, i32 020 %2 = load atomic i16, ptr %1 seq_cst, align 221 ret i8 022}23 24