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1; RUN: llc -O1 < %s -mtriple=avr | FileCheck %s2 3; This test ensures that the Select8/Select16 expansion4; pass inserts an unconditional branch to the previous adjacent5; basic block when inserting new basic blocks when the6; prior block has a fallthrough.7;8; Before this bug was fixed, Select8/Select16 expansion9; would leave a dangling fallthrough to an undefined block.10;11; The BranchFolding pass would later rearrange the basic12; blocks based on predecessor/successor list assumptions13; which were made incorrect due to the invalid Select14; expansion.15 16; More information in17; https://github.com/avr-rust/rust/issues/123.18 19%UInt8 = type <{ i8 }>20%UInt32 = type <{ i32 }>21%Sb = type <{ i1 }>22 23@delayFactor = hidden global %UInt8 zeroinitializer, align 124@delay = hidden global %UInt32 zeroinitializer, align 425@flag = hidden global %Sb zeroinitializer, align 126 27declare void @eeprom_write(i16, i8)28 29; CHECK-LABEL: update_register30define hidden void @update_register(i8 %arg, i8 %arg1) {31entry:32 ; CHECK: push [[PRELUDER:r[0-9]+]]33 ; CHECK: cpi r24, 734 switch i8 %arg, label %bb7 [35 i8 6, label %bb36 i8 7, label %bb637 ]38 39; CHECK-NOT: ret40bb: ; preds = %entry41 %tmp = icmp ugt i8 %arg1, 9042 %tmp2 = icmp ult i8 %arg1, 543 %. = select i1 %tmp2, i8 5, i8 %arg144 %tmp3 = select i1 %tmp, i8 90, i8 %.45 ; CHECK: sts delayFactor, r{{[0-9]+}}46 store i8 %tmp3, ptr @delayFactor, align 147 %tmp4 = zext i8 %tmp3 to i3248 %tmp5 = mul nuw nsw i32 %tmp4, 10049 ; CHECK: sts delay+3, r{{[0-9]+}}50 ; CHECK-NEXT: sts delay+2, r{{[0-9]+}}51 ; CHECK-NEXT: sts delay+1, r{{[0-9]+}}52 ; CHECK-NEXT: sts delay, r{{[0-9]+}}53 store i32 %tmp5, ptr @delay, align 454 tail call void @eeprom_write(i16 34, i8 %tmp3)55 br label %bb756 57bb6: ; preds = %entry58 %not. = icmp ne i8 %arg1, 059 %.2 = zext i1 %not. to i860 store i1 %not., ptr @flag, align 161 62 ; CHECK: call eeprom_write63 tail call void @eeprom_write(i16 35, i8 %.2)64 br label %bb765 66 ; CHECK: LBB0_{{[0-9]+}}67 ; CHECK: pop [[PRELUDER]]68 ; CHECK-NEXT: ret69bb7: ; preds = %bb6, %bb, %entry70 ret void71}72; CHECK-NOT: LBB0_{{[0-9]+}}:73; CHECK-LABEL: .Lfunc_end074; CHECK: .size update_register, .Lfunc_end0-update_register75