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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s3 4define signext i32 @testmsws(float %x) {5; CHECK-LABEL: testmsws:6; CHECK: ; %bb.0: ; %entry7; CHECK-NEXT: call llroundf8; CHECK-NEXT: movw r22, r189; CHECK-NEXT: movw r24, r2010; CHECK-NEXT: ret11entry:12 %0 = tail call i64 @llvm.llround.i64.f32(float %x)13 %conv = trunc i64 %0 to i3214 ret i32 %conv15}16 17define i64 @testmsxs(float %x) {18; CHECK-LABEL: testmsxs:19; CHECK: ; %bb.0: ; %entry20; CHECK-NEXT: call llroundf21; CHECK-NEXT: ret22entry:23 %0 = tail call i64 @llvm.llround.i64.f32(float %x)24 ret i64 %025}26 27define signext i32 @testmswd(double %x) {28; CHECK-LABEL: testmswd:29; CHECK: ; %bb.0: ; %entry30; CHECK-NEXT: call llround31; CHECK-NEXT: movw r22, r1832; CHECK-NEXT: movw r24, r2033; CHECK-NEXT: ret34entry:35 %0 = tail call i64 @llvm.llround.i64.f64(double %x)36 %conv = trunc i64 %0 to i3237 ret i32 %conv38}39 40define i64 @testmsxd(double %x) {41; CHECK-LABEL: testmsxd:42; CHECK: ; %bb.0: ; %entry43; CHECK-NEXT: call llround44; CHECK-NEXT: ret45entry:46 %0 = tail call i64 @llvm.llround.i64.f64(double %x)47 ret i64 %048}49 50declare i64 @llvm.llround.i64.f32(float) nounwind readnone51declare i64 @llvm.llround.i64.f64(double) nounwind readnone52