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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc < %s -mtriple=avr | FileCheck %s3 4define i8 @rotl8_1(i8 %x) {5; CHECK-LABEL: rotl8_1:6; CHECK: ; %bb.0: ; %start7; CHECK-NEXT: lsl r248; CHECK-NEXT: adc r24, r19; CHECK-NEXT: ret10start:11 %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 1)12 ret i8 %013}14 15define i8 @rotl8_3(i8 %x) {16; CHECK-LABEL: rotl8_3:17; CHECK: ; %bb.0: ; %start18; CHECK-NEXT: swap r2419; CHECK-NEXT: bst r24, 020; CHECK-NEXT: ror r2421; CHECK-NEXT: bld r24, 722; CHECK-NEXT: ret23start:24 %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)25 ret i8 %026}27 28define i8 @rotl8_5(i8 %x) {29; CHECK-LABEL: rotl8_5:30; CHECK: ; %bb.0: ; %start31; CHECK-NEXT: swap r2432; CHECK-NEXT: lsl r2433; CHECK-NEXT: adc r24, r134; CHECK-NEXT: ret35start:36 %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 5)37 ret i8 %038}39 40define i8 @rotl8_7(i8 %x) {41; CHECK-LABEL: rotl8_7:42; CHECK: ; %bb.0: ; %start43; CHECK-NEXT: bst r24, 044; CHECK-NEXT: ror r2445; CHECK-NEXT: bld r24, 746; CHECK-NEXT: ret47start:48 %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 7)49 ret i8 %050}51 52define i8 @rotl8_dyn(i8 %x, i8 %y) {53; CHECK-LABEL: rotl8_dyn:54; CHECK: ; %bb.0: ; %start55; CHECK-NEXT: andi r22, 756; CHECK-NEXT: dec r2257; CHECK-NEXT: brmi .LBB4_258; CHECK-NEXT: .LBB4_1: ; %start59; CHECK-NEXT: ; =>This Inner Loop Header: Depth=160; CHECK-NEXT: lsl r2461; CHECK-NEXT: adc r24, r162; CHECK-NEXT: dec r2263; CHECK-NEXT: brpl .LBB4_164; CHECK-NEXT: .LBB4_2: ; %start65; CHECK-NEXT: ret66start:67 %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 %y)68 ret i8 %069}70 71define i8 @rotr8_1(i8 %x) {72; CHECK-LABEL: rotr8_1:73; CHECK: ; %bb.0: ; %start74; CHECK-NEXT: bst r24, 075; CHECK-NEXT: ror r2476; CHECK-NEXT: bld r24, 777; CHECK-NEXT: ret78start:79 %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 1)80 ret i8 %081}82 83define i8 @rotr8_3(i8 %x) {84; CHECK-LABEL: rotr8_3:85; CHECK: ; %bb.0: ; %start86; CHECK-NEXT: swap r2487; CHECK-NEXT: lsl r2488; CHECK-NEXT: adc r24, r189; CHECK-NEXT: ret90start:91 %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)92 ret i8 %093}94 95define i8 @rotr8_5(i8 %x) {96; CHECK-LABEL: rotr8_5:97; CHECK: ; %bb.0: ; %start98; CHECK-NEXT: swap r2499; CHECK-NEXT: bst r24, 0100; CHECK-NEXT: ror r24101; CHECK-NEXT: bld r24, 7102; CHECK-NEXT: ret103start:104 %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 5)105 ret i8 %0106}107 108define i8 @rotr8_7(i8 %x) {109; CHECK-LABEL: rotr8_7:110; CHECK: ; %bb.0: ; %start111; CHECK-NEXT: lsl r24112; CHECK-NEXT: adc r24, r1113; CHECK-NEXT: ret114start:115 %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 7)116 ret i8 %0117}118 119define i8 @rotr8_dyn(i8 %x, i8 %y) {120; CHECK-LABEL: rotr8_dyn:121; CHECK: ; %bb.0: ; %start122; CHECK-NEXT: andi r22, 7123; CHECK-NEXT: dec r22124; CHECK-NEXT: brmi .LBB9_2125; CHECK-NEXT: .LBB9_1: ; %start126; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1127; CHECK-NEXT: bst r24, 0128; CHECK-NEXT: ror r24129; CHECK-NEXT: bld r24, 7130; CHECK-NEXT: dec r22131; CHECK-NEXT: brpl .LBB9_1132; CHECK-NEXT: .LBB9_2: ; %start133; CHECK-NEXT: ret134start:135 %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 %y)136 ret i8 %0137}138 139define i16 @rotl16(i16 %x) {140; CHECK-LABEL: rotl16:141; CHECK: ; %bb.0: ; %start142; CHECK-NEXT: mov r18, r24143; CHECK-NEXT: mov r19, r25144; CHECK-NEXT: lsl r18145; CHECK-NEXT: rol r19146; CHECK-NEXT: lsl r18147; CHECK-NEXT: rol r19148; CHECK-NEXT: mov r24, r25149; CHECK-NEXT: swap r24150; CHECK-NEXT: andi r24, 15151; CHECK-NEXT: clr r25152; CHECK-NEXT: lsr r24153; CHECK-NEXT: lsr r24154; CHECK-NEXT: or r24, r18155; CHECK-NEXT: or r25, r19156; CHECK-NEXT: ret157start:158 %0 = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 2)159 ret i16 %0160}161 162define i16 @rotr16(i16 %x) {163; CHECK-LABEL: rotr16:164; CHECK: ; %bb.0: ; %start165; CHECK-NEXT: mov r18, r24166; CHECK-NEXT: mov r19, r25167; CHECK-NEXT: lsr r19168; CHECK-NEXT: ror r18169; CHECK-NEXT: lsr r19170; CHECK-NEXT: ror r18171; CHECK-NEXT: mov r25, r24172; CHECK-NEXT: swap r25173; CHECK-NEXT: andi r25, 240174; CHECK-NEXT: clr r24175; CHECK-NEXT: lsl r25176; CHECK-NEXT: lsl r25177; CHECK-NEXT: or r24, r18178; CHECK-NEXT: or r25, r19179; CHECK-NEXT: ret180start:181 %0 = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 2)182 ret i16 %0183}184 185define i32 @rotl32(i32 %x) {186; CHECK-LABEL: rotl32:187; CHECK: ; %bb.0: ; %start188; CHECK-NEXT: mov r20, r22189; CHECK-NEXT: mov r21, r23190; CHECK-NEXT: lsl r20191; CHECK-NEXT: rol r21192; CHECK-NEXT: lsl r20193; CHECK-NEXT: rol r21194; CHECK-NEXT: mov r18, r24195; CHECK-NEXT: mov r19, r25196; CHECK-NEXT: mov r18, r19197; CHECK-NEXT: swap r18198; CHECK-NEXT: andi r18, 15199; CHECK-NEXT: clr r19200; CHECK-NEXT: lsr r18201; CHECK-NEXT: lsr r18202; CHECK-NEXT: or r18, r20203; CHECK-NEXT: or r19, r21204; CHECK-NEXT: lsl r24205; CHECK-NEXT: rol r25206; CHECK-NEXT: lsl r24207; CHECK-NEXT: rol r25208; CHECK-NEXT: mov r22, r23209; CHECK-NEXT: swap r22210; CHECK-NEXT: andi r22, 15211; CHECK-NEXT: clr r23212; CHECK-NEXT: lsr r22213; CHECK-NEXT: lsr r22214; CHECK-NEXT: or r24, r22215; CHECK-NEXT: or r25, r23216; CHECK-NEXT: mov r22, r18217; CHECK-NEXT: mov r23, r19218; CHECK-NEXT: ret219start:220 %0 = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 2)221 ret i32 %0222}223 224define i32 @rotr32(i32 %x) {225; CHECK-LABEL: rotr32:226; CHECK: ; %bb.0: ; %start227; CHECK-NEXT: mov r20, r22228; CHECK-NEXT: mov r21, r23229; CHECK-NEXT: lsr r21230; CHECK-NEXT: ror r20231; CHECK-NEXT: lsr r21232; CHECK-NEXT: ror r20233; CHECK-NEXT: mov r18, r24234; CHECK-NEXT: mov r19, r25235; CHECK-NEXT: mov r19, r18236; CHECK-NEXT: swap r19237; CHECK-NEXT: andi r19, 240238; CHECK-NEXT: clr r18239; CHECK-NEXT: lsl r19240; CHECK-NEXT: lsl r19241; CHECK-NEXT: or r18, r20242; CHECK-NEXT: or r19, r21243; CHECK-NEXT: lsr r25244; CHECK-NEXT: ror r24245; CHECK-NEXT: lsr r25246; CHECK-NEXT: ror r24247; CHECK-NEXT: mov r23, r22248; CHECK-NEXT: swap r23249; CHECK-NEXT: andi r23, 240250; CHECK-NEXT: clr r22251; CHECK-NEXT: lsl r23252; CHECK-NEXT: lsl r23253; CHECK-NEXT: or r24, r22254; CHECK-NEXT: or r25, r23255; CHECK-NEXT: mov r22, r18256; CHECK-NEXT: mov r23, r19257; CHECK-NEXT: ret258start:259 %0 = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 2)260 ret i32 %0261}262 263declare i8 @llvm.fshl.i8(i8, i8, i8)264declare i8 @llvm.fshr.i8(i8, i8, i8)265 266declare i16 @llvm.fshl.i16(i16, i16, i16)267declare i16 @llvm.fshr.i16(i16, i16, i16)268 269declare i32 @llvm.fshl.i32(i32, i32, i32)270declare i32 @llvm.fshr.i32(i32, i32, i32)271