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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=avr-none -verify-machineinstrs | FileCheck %s3 4; Optimize for speed.5define i8 @shift_i8_i8_speed(i8 %a, i8 %b) {6; CHECK-LABEL: shift_i8_i8_speed:7; CHECK: ; %bb.0:8; CHECK-NEXT: dec r229; CHECK-NEXT: brmi .LBB0_210; CHECK-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=111; CHECK-NEXT: lsl r2412; CHECK-NEXT: dec r2213; CHECK-NEXT: brpl .LBB0_114; CHECK-NEXT: .LBB0_2:15; CHECK-NEXT: ret16 %result = shl i8 %a, %b17 ret i8 %result18}19 20; Optimize for size (producing slightly smaller code).21define i8 @shift_i8_i8_size(i8 %a, i8 %b) optsize {22; CHECK-LABEL: shift_i8_i8_size:23; CHECK: ; %bb.0:24; CHECK-NEXT: .LBB1_1: ; =>This Inner Loop Header: Depth=125; CHECK-NEXT: dec r2226; CHECK-NEXT: brmi .LBB1_327; CHECK-NEXT: ; %bb.2: ; in Loop: Header=BB1_1 Depth=128; CHECK-NEXT: lsl r2429; CHECK-NEXT: rjmp .LBB1_130; CHECK-NEXT: .LBB1_3:31; CHECK-NEXT: ret32 %result = shl i8 %a, %b33 ret i8 %result34}35 36define i16 @shift_i16_i16(i16 %a, i16 %b) {37; CHECK-LABEL: shift_i16_i16:38; CHECK: ; %bb.0:39; CHECK-NEXT: dec r2240; CHECK-NEXT: brmi .LBB2_241; CHECK-NEXT: .LBB2_1: ; =>This Inner Loop Header: Depth=142; CHECK-NEXT: lsl r2443; CHECK-NEXT: rol r2544; CHECK-NEXT: dec r2245; CHECK-NEXT: brpl .LBB2_146; CHECK-NEXT: .LBB2_2:47; CHECK-NEXT: ret48 %result = shl i16 %a, %b49 ret i16 %result50}51 52define i64 @shift_i64_i64(i64 %a, i64 %b) {53; CHECK-LABEL: shift_i64_i64:54; CHECK: ; %bb.0:55; CHECK-NEXT: push r1656; CHECK-NEXT: push r1757; CHECK-NEXT: mov r30, r1058; CHECK-NEXT: mov r31, r1159; CHECK-NEXT: cpi r30, 060; CHECK-NEXT: breq .LBB3_361; CHECK-NEXT: ; %bb.1: ; %shift.loop.preheader62; CHECK-NEXT: mov r27, r163; CHECK-NEXT: mov r16, r2764; CHECK-NEXT: mov r17, r2765; CHECK-NEXT: .LBB3_2: ; %shift.loop66; CHECK-NEXT: ; =>This Inner Loop Header: Depth=167; CHECK-NEXT: mov r31, r2168; CHECK-NEXT: lsl r3169; CHECK-NEXT: mov r26, r2770; CHECK-NEXT: rol r2671; CHECK-NEXT: lsl r2272; CHECK-NEXT: rol r2373; CHECK-NEXT: rol r2474; CHECK-NEXT: rol r2575; CHECK-NEXT: or r24, r1676; CHECK-NEXT: or r25, r1777; CHECK-NEXT: or r22, r2678; CHECK-NEXT: or r23, r2779; CHECK-NEXT: lsl r1880; CHECK-NEXT: rol r1981; CHECK-NEXT: rol r2082; CHECK-NEXT: rol r2183; CHECK-NEXT: dec r3084; CHECK-NEXT: cpi r30, 085; CHECK-NEXT: brne .LBB3_286; CHECK-NEXT: .LBB3_3: ; %shift.done87; CHECK-NEXT: pop r1788; CHECK-NEXT: pop r1689; CHECK-NEXT: ret90 %result = shl i64 %a, %b91 ret i64 %result92}93 94define i8 @lsl_i8_1(i8 %a) {95; CHECK-LABEL: lsl_i8_1:96; CHECK: ; %bb.0:97; CHECK-NEXT: lsl r2498; CHECK-NEXT: ret99 %res = shl i8 %a, 1100 ret i8 %res101}102 103define i8 @lsl_i8_2(i8 %a) {104; CHECK-LABEL: lsl_i8_2:105; CHECK: ; %bb.0:106; CHECK-NEXT: lsl r24107; CHECK-NEXT: lsl r24108; CHECK-NEXT: ret109 %res = shl i8 %a, 2110 ret i8 %res111}112 113define i8 @lsl_i8_3(i8 %a) {114; CHECK-LABEL: lsl_i8_3:115; CHECK: ; %bb.0:116; CHECK-NEXT: lsl r24117; CHECK-NEXT: lsl r24118; CHECK-NEXT: lsl r24119; CHECK-NEXT: ret120 %res = shl i8 %a, 3121 ret i8 %res122}123 124define i8 @lsl_i8_4(i8 %a) {125; CHECK-LABEL: lsl_i8_4:126; CHECK: ; %bb.0:127; CHECK-NEXT: swap r24128; CHECK-NEXT: andi r24, -16129; CHECK-NEXT: ret130 %res = shl i8 %a, 4131 ret i8 %res132}133 134define i8 @lsl_i8_5(i8 %a) {135; CHECK-LABEL: lsl_i8_5:136; CHECK: ; %bb.0:137; CHECK-NEXT: swap r24138; CHECK-NEXT: andi r24, -16139; CHECK-NEXT: lsl r24140; CHECK-NEXT: ret141 %res = shl i8 %a, 5142 ret i8 %res143}144 145define i8 @lsl_i8_6(i8 %a) {146; CHECK-LABEL: lsl_i8_6:147; CHECK: ; %bb.0:148; CHECK-NEXT: swap r24149; CHECK-NEXT: andi r24, -16150; CHECK-NEXT: lsl r24151; CHECK-NEXT: lsl r24152; CHECK-NEXT: ret153 %res = shl i8 %a, 6154 ret i8 %res155}156 157define i8 @lsr_i8_1(i8 %a) {158; CHECK-LABEL: lsr_i8_1:159; CHECK: ; %bb.0:160; CHECK-NEXT: lsr r24161; CHECK-NEXT: ret162 %res = lshr i8 %a, 1163 ret i8 %res164}165 166define i8 @lsr_i8_2(i8 %a) {167; CHECK-LABEL: lsr_i8_2:168; CHECK: ; %bb.0:169; CHECK-NEXT: lsr r24170; CHECK-NEXT: lsr r24171; CHECK-NEXT: ret172 %res = lshr i8 %a, 2173 ret i8 %res174}175 176define i8 @lsr_i8_3(i8 %a) {177; CHECK-LABEL: lsr_i8_3:178; CHECK: ; %bb.0:179; CHECK-NEXT: lsr r24180; CHECK-NEXT: lsr r24181; CHECK-NEXT: lsr r24182; CHECK-NEXT: ret183 %res = lshr i8 %a, 3184 ret i8 %res185}186 187define i8 @lsr_i8_4(i8 %a) {188; CHECK-LABEL: lsr_i8_4:189; CHECK: ; %bb.0:190; CHECK-NEXT: swap r24191; CHECK-NEXT: andi r24, 15192; CHECK-NEXT: ret193 %res = lshr i8 %a, 4194 ret i8 %res195}196 197define i8 @lsr_i8_5(i8 %a) {198; CHECK-LABEL: lsr_i8_5:199; CHECK: ; %bb.0:200; CHECK-NEXT: swap r24201; CHECK-NEXT: andi r24, 15202; CHECK-NEXT: lsr r24203; CHECK-NEXT: ret204 %res = lshr i8 %a, 5205 ret i8 %res206}207 208define i8 @lsr_i8_6(i8 %a) {209; CHECK-LABEL: lsr_i8_6:210; CHECK: ; %bb.0:211; CHECK-NEXT: swap r24212; CHECK-NEXT: andi r24, 15213; CHECK-NEXT: lsr r24214; CHECK-NEXT: lsr r24215; CHECK-NEXT: ret216 %res = lshr i8 %a, 6217 ret i8 %res218}219 220define i8 @lsl_i8_7(i8 %a) {221; CHECK-LABEL: lsl_i8_7:222; CHECK: ; %bb.0:223; CHECK-NEXT: ror r24224; CHECK-NEXT: clr r24225; CHECK-NEXT: ror r24226; CHECK-NEXT: ret227 %result = shl i8 %a, 7228 ret i8 %result229}230 231define i8 @lsr_i8_7(i8 %a) {232; CHECK-LABEL: lsr_i8_7:233; CHECK: ; %bb.0:234; CHECK-NEXT: rol r24235; CHECK-NEXT: clr r24236; CHECK-NEXT: rol r24237; CHECK-NEXT: ret238 %result = lshr i8 %a, 7239 ret i8 %result240}241 242define i8 @asr_i8_6(i8 %a) {243; CHECK-LABEL: asr_i8_6:244; CHECK: ; %bb.0:245; CHECK-NEXT: bst r24, 6246; CHECK-NEXT: lsl r24247; CHECK-NEXT: sbc r24, r24248; CHECK-NEXT: bld r24, 0249; CHECK-NEXT: ret250 %result = ashr i8 %a, 6251 ret i8 %result252}253 254define i8 @asr_i8_7(i8 %a) {255; CHECK-LABEL: asr_i8_7:256; CHECK: ; %bb.0:257; CHECK-NEXT: lsl r24258; CHECK-NEXT: sbc r24, r24259; CHECK-NEXT: ret260 %result = ashr i8 %a, 7261 ret i8 %result262}263 264define i16 @lsl_i16_5(i16 %a) {265; CHECK-LABEL: lsl_i16_5:266; CHECK: ; %bb.0:267; CHECK-NEXT: swap r25268; CHECK-NEXT: swap r24269; CHECK-NEXT: andi r25, 240270; CHECK-NEXT: eor r25, r24271; CHECK-NEXT: andi r24, 240272; CHECK-NEXT: eor r25, r24273; CHECK-NEXT: lsl r24274; CHECK-NEXT: rol r25275; CHECK-NEXT: ret276 %result = shl i16 %a, 5277 ret i16 %result278}279 280define i16 @lsl_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {281; CHECK-LABEL: lsl_i16_6:282; CHECK: ; %bb.0:283; CHECK-NEXT: mov r24, r14284; CHECK-NEXT: mov r25, r15285; CHECK-NEXT: swap r25286; CHECK-NEXT: swap r24287; CHECK-NEXT: andi r25, 240288; CHECK-NEXT: eor r25, r24289; CHECK-NEXT: andi r24, 240290; CHECK-NEXT: eor r25, r24291; CHECK-NEXT: lsl r24292; CHECK-NEXT: rol r25293; CHECK-NEXT: lsl r24294; CHECK-NEXT: rol r25295; CHECK-NEXT: ret296 %result = shl i16 %f, 6297 ret i16 %result298}299 300define i16 @lsl_i16_9(i16 %a) {301; CHECK-LABEL: lsl_i16_9:302; CHECK: ; %bb.0:303; CHECK-NEXT: mov r25, r24304; CHECK-NEXT: clr r24305; CHECK-NEXT: lsl r25306; CHECK-NEXT: ret307 %result = shl i16 %a, 9308 ret i16 %result309}310 311define i16 @lsl_i16_13(i16 %a) {312; CHECK-LABEL: lsl_i16_13:313; CHECK: ; %bb.0:314; CHECK-NEXT: mov r25, r24315; CHECK-NEXT: swap r25316; CHECK-NEXT: andi r25, 240317; CHECK-NEXT: clr r24318; CHECK-NEXT: lsl r25319; CHECK-NEXT: ret320 %result = shl i16 %a, 13321 ret i16 %result322}323 324define i16 @lsr_i16_5(i16 %a) {325; CHECK-LABEL: lsr_i16_5:326; CHECK: ; %bb.0:327; CHECK-NEXT: swap r25328; CHECK-NEXT: swap r24329; CHECK-NEXT: andi r24, 15330; CHECK-NEXT: eor r24, r25331; CHECK-NEXT: andi r25, 15332; CHECK-NEXT: eor r24, r25333; CHECK-NEXT: lsr r25334; CHECK-NEXT: ror r24335; CHECK-NEXT: ret336 %result = lshr i16 %a, 5337 ret i16 %result338}339 340define i16 @lsr_i16_6(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f) {341; CHECK-LABEL: lsr_i16_6:342; CHECK: ; %bb.0:343; CHECK-NEXT: mov r24, r14344; CHECK-NEXT: mov r25, r15345; CHECK-NEXT: swap r25346; CHECK-NEXT: swap r24347; CHECK-NEXT: andi r24, 15348; CHECK-NEXT: eor r24, r25349; CHECK-NEXT: andi r25, 15350; CHECK-NEXT: eor r24, r25351; CHECK-NEXT: lsr r25352; CHECK-NEXT: ror r24353; CHECK-NEXT: lsr r25354; CHECK-NEXT: ror r24355; CHECK-NEXT: ret356 %result = lshr i16 %f, 6357 ret i16 %result358}359 360define i16 @lsr_i16_9(i16 %a) {361; CHECK-LABEL: lsr_i16_9:362; CHECK: ; %bb.0:363; CHECK-NEXT: mov r24, r25364; CHECK-NEXT: clr r25365; CHECK-NEXT: lsr r24366; CHECK-NEXT: ret367 %result = lshr i16 %a, 9368 ret i16 %result369}370 371define i16 @lsr_i16_13(i16 %a) {372; CHECK-LABEL: lsr_i16_13:373; CHECK: ; %bb.0:374; CHECK-NEXT: mov r24, r25375; CHECK-NEXT: swap r24376; CHECK-NEXT: andi r24, 15377; CHECK-NEXT: clr r25378; CHECK-NEXT: lsr r24379; CHECK-NEXT: ret380 %result = lshr i16 %a, 13381 ret i16 %result382}383 384define i16 @asr_i16_7(i16 %a) {385; CHECK-LABEL: asr_i16_7:386; CHECK: ; %bb.0:387; CHECK-NEXT: lsl r24388; CHECK-NEXT: mov r24, r25389; CHECK-NEXT: rol r24390; CHECK-NEXT: sbc r25, r25391; CHECK-NEXT: ret392 %result = ashr i16 %a, 7393 ret i16 %result394}395 396define i16 @asr_i16_9(i16 %a) {397; CHECK-LABEL: asr_i16_9:398; CHECK: ; %bb.0:399; CHECK-NEXT: mov r24, r25400; CHECK-NEXT: lsl r25401; CHECK-NEXT: sbc r25, r25402; CHECK-NEXT: asr r24403; CHECK-NEXT: ret404 %result = ashr i16 %a, 9405 ret i16 %result406}407 408define i16 @asr_i16_12(i16 %a) {409; CHECK-LABEL: asr_i16_12:410; CHECK: ; %bb.0:411; CHECK-NEXT: mov r24, r25412; CHECK-NEXT: lsl r25413; CHECK-NEXT: sbc r25, r25414; CHECK-NEXT: asr r24415; CHECK-NEXT: asr r24416; CHECK-NEXT: asr r24417; CHECK-NEXT: asr r24418; CHECK-NEXT: ret419 %result = ashr i16 %a, 12420 ret i16 %result421}422 423define i16 @asr_i16_14(i16 %a) {424; CHECK-LABEL: asr_i16_14:425; CHECK: ; %bb.0:426; CHECK-NEXT: lsl r25427; CHECK-NEXT: sbc r24, r24428; CHECK-NEXT: lsl r25429; CHECK-NEXT: mov r25, r24430; CHECK-NEXT: rol r24431; CHECK-NEXT: ret432 %result = ashr i16 %a, 14433 ret i16 %result434}435 436define i16 @asr_i16_15(i16 %a) {437; CHECK-LABEL: asr_i16_15:438; CHECK: ; %bb.0:439; CHECK-NEXT: lsl r25440; CHECK-NEXT: sbc r25, r25441; CHECK-NEXT: mov r24, r25442; CHECK-NEXT: ret443 %result = ashr i16 %a, 15444 ret i16 %result445}446