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1; RUN: llc < %s -mtriple=bpfeb -mcpu=v1 -show-mc-encoding | FileCheck %s2; test big endian3 4define void @test() #0 {5entry:6; CHECK: test:7 8; CHECK: r1 = 123 # encoding: [0xb7,0x10,0x00,0x00,0x00,0x00,0x00,0x7b]9; CHECK: call f_i1610 call void @f_i16(i16 123)11 12; CHECK: r1 = 12345678 # encoding: [0xb7,0x10,0x00,0x00,0x00,0xbc,0x61,0x4e]13; CHECK: call f_i3214 call void @f_i32(i32 12345678)15 16; CHECK: r1 = 72623859790382856 ll # encoding: [0x18,0x10,0x00,0x00,0x05,0x06,0x07,0x08,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04]17; CHECK: call f_i6418 call void @f_i64(i64 72623859790382856)19 20; CHECK: r1 = 123421; CHECK: r2 = 567822; CHECK: call f_i32_i3223 call void @f_i32_i32(i32 1234, i32 5678)24 25; CHECK: r1 = 226; CHECK: r2 = 327; CHECK: r3 = 428; CHECK: call f_i16_i32_i1629 call void @f_i16_i32_i16(i16 2, i32 3, i16 4)30 31; CHECK: r1 = 532; CHECK: r2 = 7262385979038285 ll33; CHECK: r3 = 634; CHECK: call f_i16_i64_i1635 call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6)36 37 ret void38}39 40@g_i16 = common global i16 0, align 241@g_i32 = common global i32 0, align 242@g_i64 = common global i64 0, align 443 44define void @f_i16(i16 %a) #0 {45; CHECK: f_i16:46; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]47 store volatile i16 %a, ptr @g_i16, align 248 ret void49}50 51define void @f_i32(i32 %a) #0 {52; CHECK: f_i32:53; CHECK: *(u16 *)(r2 + 2) = r1 # encoding: [0x6b,0x21,0x00,0x02,0x00,0x00,0x00,0x00]54; CHECK: *(u16 *)(r2 + 0) = r1 # encoding: [0x6b,0x21,0x00,0x00,0x00,0x00,0x00,0x00]55 store volatile i32 %a, ptr @g_i32, align 256 ret void57}58 59define void @f_i64(i64 %a) #0 {60; CHECK: f_i64:61; CHECK: *(u32 *)(r2 + 4) = r1 # encoding: [0x63,0x21,0x00,0x04,0x00,0x00,0x00,0x00]62; CHECK: *(u32 *)(r2 + 0) = r163 store volatile i64 %a, ptr @g_i64, align 264 ret void65}66 67define void @f_i32_i32(i32 %a, i32 %b) #0 {68; CHECK: f_i32_i32:69; CHECK: *(u32 *)(r3 + 0) = r170 store volatile i32 %a, ptr @g_i32, align 471; CHECK: *(u32 *)(r3 + 0) = r272 store volatile i32 %b, ptr @g_i32, align 473 ret void74}75 76define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 {77; CHECK: f_i16_i32_i16:78; CHECK: *(u16 *)(r4 + 0) = r179 store volatile i16 %a, ptr @g_i16, align 280; CHECK: *(u32 *)(r1 + 0) = r281 store volatile i32 %b, ptr @g_i32, align 482; CHECK: *(u16 *)(r4 + 0) = r383 store volatile i16 %c, ptr @g_i16, align 284 ret void85}86 87define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 {88; CHECK: f_i16_i64_i16:89; CHECK: *(u16 *)(r4 + 0) = r190 store volatile i16 %a, ptr @g_i16, align 291; CHECK: *(u64 *)(r1 + 0) = r2 # encoding: [0x7b,0x12,0x00,0x00,0x00,0x00,0x00,0x00]92 store volatile i64 %b, ptr @g_i64, align 893; CHECK: *(u16 *)(r4 + 0) = r394 store volatile i16 %c, ptr @g_i16, align 295 ret void96}97