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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2 3; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF4; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF25 6 7define float @faddRR(float %x, float %y) {8;9; CHECK-SF-LABEL: faddRR:10; CHECK-SF: # %bb.0: # %entry11; CHECK-SF-NEXT: fadds vr0, vr1, vr012; CHECK-SF-NEXT: rts1613;14; CHECK-SF2-LABEL: faddRR:15; CHECK-SF2: # %bb.0: # %entry16; CHECK-SF2-NEXT: fadd.32 vr0, vr1, vr017; CHECK-SF2-NEXT: rts1618 19entry:20 %fadd = fadd float %y, %x21 ret float %fadd22}23 24define float @faddRI(float %x) {25;26; CHECK-SF-LABEL: faddRI:27; CHECK-SF: # %bb.0: # %entry28; CHECK-SF-NEXT: movih32 a0, 1667229; CHECK-SF-NEXT: fmtvrl vr1, a030; CHECK-SF-NEXT: fadds vr0, vr0, vr131; CHECK-SF-NEXT: rts1632;33; CHECK-SF2-LABEL: faddRI:34; CHECK-SF2: # %bb.0: # %entry35; CHECK-SF2-NEXT: movih32 a0, 1667236; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a037; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr138; CHECK-SF2-NEXT: rts1639 40entry:41 %fadd = fadd float %x, 10.042 ret float %fadd43}44 45define float @faddRI_X(float %x) {46;47; CHECK-SF-LABEL: faddRI_X:48; CHECK-SF: # %bb.0: # %entry49; CHECK-SF-NEXT: movih32 a0, 1779250; CHECK-SF-NEXT: ori32 a0, a0, 204851; CHECK-SF-NEXT: fmtvrl vr1, a052; CHECK-SF-NEXT: fadds vr0, vr0, vr153; CHECK-SF-NEXT: rts1654;55; CHECK-SF2-LABEL: faddRI_X:56; CHECK-SF2: # %bb.0: # %entry57; CHECK-SF2-NEXT: movih32 a0, 1779258; CHECK-SF2-NEXT: ori32 a0, a0, 204859; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a060; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr161; CHECK-SF2-NEXT: rts1662 63entry:64 %fadd = fadd float %x, 4097.065 ret float %fadd66}67 68define float @fsubRR(float %x, float %y) {69;70; CHECK-SF-LABEL: fsubRR:71; CHECK-SF: # %bb.0: # %entry72; CHECK-SF-NEXT: fsubs vr0, vr1, vr073; CHECK-SF-NEXT: rts1674;75; CHECK-SF2-LABEL: fsubRR:76; CHECK-SF2: # %bb.0: # %entry77; CHECK-SF2-NEXT: fsub.32 vr0, vr1, vr078; CHECK-SF2-NEXT: rts1679 80 81entry:82 %fsub = fsub float %y, %x83 ret float %fsub84}85 86define float @fsubRI(float %x) {87;88; CHECK-SF-LABEL: fsubRI:89; CHECK-SF: # %bb.0: # %entry90; CHECK-SF-NEXT: movih32 a0, 4944091; CHECK-SF-NEXT: fmtvrl vr1, a092; CHECK-SF-NEXT: fadds vr0, vr0, vr193; CHECK-SF-NEXT: rts1694;95; CHECK-SF2-LABEL: fsubRI:96; CHECK-SF2: # %bb.0: # %entry97; CHECK-SF2-NEXT: movih32 a0, 4944098; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a099; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1100; CHECK-SF2-NEXT: rts16101 102entry:103 %fsub = fsub float %x, 10.0104 ret float %fsub105}106 107define float @fsubRI_X(float %x) {108;109; CHECK-SF-LABEL: fsubRI_X:110; CHECK-SF: # %bb.0: # %entry111; CHECK-SF-NEXT: movih32 a0, 50560112; CHECK-SF-NEXT: ori32 a0, a0, 2048113; CHECK-SF-NEXT: fmtvrl vr1, a0114; CHECK-SF-NEXT: fadds vr0, vr0, vr1115; CHECK-SF-NEXT: rts16116;117; CHECK-SF2-LABEL: fsubRI_X:118; CHECK-SF2: # %bb.0: # %entry119; CHECK-SF2-NEXT: movih32 a0, 50560120; CHECK-SF2-NEXT: ori32 a0, a0, 2048121; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0122; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1123; CHECK-SF2-NEXT: rts16124 125entry:126 %fsub = fsub float %x, 4097.0127 ret float %fsub128}129 130define float @fmulRR(float %x, float %y) {131;132; CHECK-SF-LABEL: fmulRR:133; CHECK-SF: # %bb.0: # %entry134; CHECK-SF-NEXT: fmuls vr0, vr1, vr0135; CHECK-SF-NEXT: rts16136;137; CHECK-SF2-LABEL: fmulRR:138; CHECK-SF2: # %bb.0: # %entry139; CHECK-SF2-NEXT: fmul.32 vr0, vr1, vr0140; CHECK-SF2-NEXT: rts16141 142entry:143 %fmul = fmul float %y, %x144 ret float %fmul145}146 147define float @fnmulRR_a(float %x, float %y) {148;149; CHECK-SF-LABEL: fnmulRR_a:150; CHECK-SF: # %bb.0: # %entry151; CHECK-SF-NEXT: fnmuls vr0, vr1, vr0152; CHECK-SF-NEXT: rts16153;154; CHECK-SF2-LABEL: fnmulRR_a:155; CHECK-SF2: # %bb.0: # %entry156; CHECK-SF2-NEXT: fnmul.32 vr0, vr1, vr0157; CHECK-SF2-NEXT: rts16158 159entry:160 %z = fneg float %y161 %fnmul = fmul float %z, %x162 ret float %fnmul163}164 165define float @fnmulRR_b(float %x, float %y) {166; CHECK-SF-LABEL: fnmulRR_b:167; CHECK-SF: # %bb.0: # %entry168; CHECK-SF-NEXT: fnmuls vr0, vr0, vr1169; CHECK-SF-NEXT: rts16170;171; CHECK-SF2-LABEL: fnmulRR_b:172; CHECK-SF2: # %bb.0: # %entry173; CHECK-SF2-NEXT: fnmul.32 vr0, vr0, vr1174; CHECK-SF2-NEXT: rts16175entry:176 %z = fneg float %x177 %fnmul = fmul float %y, %z178 ret float %fnmul179}180 181define float @fmulRI(float %x) {182;183; CHECK-SF-LABEL: fmulRI:184; CHECK-SF: # %bb.0: # %entry185; CHECK-SF-NEXT: movih32 a0, 16672186; CHECK-SF-NEXT: fmtvrl vr1, a0187; CHECK-SF-NEXT: fmuls vr0, vr0, vr1188; CHECK-SF-NEXT: rts16189;190; CHECK-SF2-LABEL: fmulRI:191; CHECK-SF2: # %bb.0: # %entry192; CHECK-SF2-NEXT: movih32 a0, 16672193; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0194; CHECK-SF2-NEXT: fmul.32 vr0, vr0, vr1195; CHECK-SF2-NEXT: rts16196 197entry:198 %fmul = fmul float %x, 10.0199 ret float %fmul200}201 202define float @fmulRI_X(float %x) {203;204; CHECK-SF-LABEL: fmulRI_X:205; CHECK-SF: # %bb.0: # %entry206; CHECK-SF-NEXT: movih32 a0, 17792207; CHECK-SF-NEXT: ori32 a0, a0, 2048208; CHECK-SF-NEXT: fmtvrl vr1, a0209; CHECK-SF-NEXT: fmuls vr0, vr0, vr1210; CHECK-SF-NEXT: rts16211;212; CHECK-SF2-LABEL: fmulRI_X:213; CHECK-SF2: # %bb.0: # %entry214; CHECK-SF2-NEXT: movih32 a0, 17792215; CHECK-SF2-NEXT: ori32 a0, a0, 2048216; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0217; CHECK-SF2-NEXT: fmul.32 vr0, vr0, vr1218; CHECK-SF2-NEXT: rts16219 220entry:221 %fmul = fmul float %x, 4097.0222 ret float %fmul223}224 225define float @fdivRR(float %x, float %y) {226;227; CHECK-SF-LABEL: fdivRR:228; CHECK-SF: # %bb.0: # %entry229; CHECK-SF-NEXT: fdivs vr0, vr1, vr0230; CHECK-SF-NEXT: rts16231;232; CHECK-SF2-LABEL: fdivRR:233; CHECK-SF2: # %bb.0: # %entry234; CHECK-SF2-NEXT: fdiv.32 vr0, vr1, vr0235; CHECK-SF2-NEXT: rts16236 237 238entry:239 %fdiv = fdiv float %y, %x240 ret float %fdiv241}242 243define float @fdivRI(float %x) {244;245; CHECK-SF-LABEL: fdivRI:246; CHECK-SF: # %bb.0: # %entry247; CHECK-SF-NEXT: movih32 a0, 16672248; CHECK-SF-NEXT: fmtvrl vr1, a0249; CHECK-SF-NEXT: fdivs vr0, vr0, vr1250; CHECK-SF-NEXT: rts16251;252; CHECK-SF2-LABEL: fdivRI:253; CHECK-SF2: # %bb.0: # %entry254; CHECK-SF2-NEXT: movih32 a0, 16672255; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0256; CHECK-SF2-NEXT: fdiv.32 vr0, vr0, vr1257; CHECK-SF2-NEXT: rts16258 259 260entry:261 %fdiv = fdiv float %x, 10.0262 ret float %fdiv263}264 265define float @fdivRI_X(float %x) {266;267; CHECK-SF-LABEL: fdivRI_X:268; CHECK-SF: # %bb.0: # %entry269; CHECK-SF-NEXT: movih32 a0, 17792270; CHECK-SF-NEXT: ori32 a0, a0, 2048271; CHECK-SF-NEXT: fmtvrl vr1, a0272; CHECK-SF-NEXT: fdivs vr0, vr0, vr1273; CHECK-SF-NEXT: rts16274;275; CHECK-SF2-LABEL: fdivRI_X:276; CHECK-SF2: # %bb.0: # %entry277; CHECK-SF2-NEXT: movih32 a0, 17792278; CHECK-SF2-NEXT: ori32 a0, a0, 2048279; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0280; CHECK-SF2-NEXT: fdiv.32 vr0, vr0, vr1281; CHECK-SF2-NEXT: rts16282 283entry:284 %fdiv = fdiv float %x, 4097.0285 ret float %fdiv286}287 288define float @fnegRR(float %x) {289;290; CHECK-SF-LABEL: fnegRR:291; CHECK-SF: # %bb.0: # %entry292; CHECK-SF-NEXT: fnegs vr0, vr0293; CHECK-SF-NEXT: rts16294;295; CHECK-SF2-LABEL: fnegRR:296; CHECK-SF2: # %bb.0: # %entry297; CHECK-SF2-NEXT: fneg.32 vr0, vr0298; CHECK-SF2-NEXT: rts16299 300entry:301 %fneg = fneg float %x302 ret float %fneg303}304