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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2 3; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF4; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF25 6;ueq7define i1 @fcmpRR_ueq(float %x, float %y) {8;9; CHECK-SF-LABEL: fcmpRR_ueq:10; CHECK-SF: # %bb.0: # %entry11; CHECK-SF-NEXT: fcmpuos vr1, vr012; CHECK-SF-NEXT: mvc32 a013; CHECK-SF-NEXT: fcmpnes vr1, vr014; CHECK-SF-NEXT: mvcv16 a115; CHECK-SF-NEXT: or16 a0, a116; CHECK-SF-NEXT: rts1617;18; CHECK-SF2-LABEL: fcmpRR_ueq:19; CHECK-SF2: # %bb.0: # %entry20; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr021; CHECK-SF2-NEXT: mvc32 a022; CHECK-SF2-NEXT: fcmpne.32 vr1, vr023; CHECK-SF2-NEXT: mvcv16 a124; CHECK-SF2-NEXT: or16 a0, a125; CHECK-SF2-NEXT: rts1626entry:27 %fcmp = fcmp ueq float %y, %x28 ret i1 %fcmp29}30 31define i1 @fcmpRI_ueq(float %x) {32;33; CHECK-SF-LABEL: fcmpRI_ueq:34; CHECK-SF: # %bb.0: # %entry35; CHECK-SF-NEXT: movih32 a0, 4944036; CHECK-SF-NEXT: fmtvrl vr1, a037; CHECK-SF-NEXT: fcmpnes vr0, vr138; CHECK-SF-NEXT: mvcv16 a039; CHECK-SF-NEXT: fcmpuos vr0, vr040; CHECK-SF-NEXT: mvc32 a141; CHECK-SF-NEXT: or16 a0, a142; CHECK-SF-NEXT: rts1643;44; CHECK-SF2-LABEL: fcmpRI_ueq:45; CHECK-SF2: # %bb.0: # %entry46; CHECK-SF2-NEXT: movih32 a0, 4944047; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a048; CHECK-SF2-NEXT: fcmpne.32 vr0, vr149; CHECK-SF2-NEXT: mvcv16 a050; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr051; CHECK-SF2-NEXT: mvc32 a152; CHECK-SF2-NEXT: or16 a0, a153; CHECK-SF2-NEXT: rts1654entry:55 %fcmp = fcmp ueq float %x, -10.056 ret i1 %fcmp57}58 59define i1 @fcmpRI_X_ueq(float %x) {60;61; CHECK-SF-LABEL: fcmpRI_X_ueq:62; CHECK-SF: # %bb.0: # %entry63; CHECK-SF-NEXT: fcmpuos vr0, vr064; CHECK-SF-NEXT: mvc32 a065; CHECK-SF-NEXT: fcmpznes vr066; CHECK-SF-NEXT: mvcv16 a167; CHECK-SF-NEXT: or16 a0, a168; CHECK-SF-NEXT: rts1669;70; CHECK-SF2-LABEL: fcmpRI_X_ueq:71; CHECK-SF2: # %bb.0: # %entry72; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr073; CHECK-SF2-NEXT: mvc32 a074; CHECK-SF2-NEXT: fcmpnez.32 vr075; CHECK-SF2-NEXT: mvcv16 a176; CHECK-SF2-NEXT: or16 a0, a177; CHECK-SF2-NEXT: rts1678entry:79 %fcmp = fcmp ueq float %x, 0.080 ret i1 %fcmp81}82 83 84;une85define i1 @fcmpRR_une(float %x, float %y) {86;87; CHECK-SF-LABEL: fcmpRR_une:88; CHECK-SF: # %bb.0: # %entry89; CHECK-SF-NEXT: fcmpnes vr1, vr090; CHECK-SF-NEXT: mvc32 a091; CHECK-SF-NEXT: rts1692;93; CHECK-SF2-LABEL: fcmpRR_une:94; CHECK-SF2: # %bb.0: # %entry95; CHECK-SF2-NEXT: fcmpne.32 vr1, vr096; CHECK-SF2-NEXT: mvc32 a097; CHECK-SF2-NEXT: rts1698entry:99 %fcmp = fcmp une float %y, %x100 ret i1 %fcmp101}102 103define i1 @fcmpRI_une(float %x) {104;105; CHECK-SF-LABEL: fcmpRI_une:106; CHECK-SF: # %bb.0: # %entry107; CHECK-SF-NEXT: movih32 a0, 49440108; CHECK-SF-NEXT: fmtvrl vr1, a0109; CHECK-SF-NEXT: fcmpnes vr0, vr1110; CHECK-SF-NEXT: mvc32 a0111; CHECK-SF-NEXT: rts16112;113; CHECK-SF2-LABEL: fcmpRI_une:114; CHECK-SF2: # %bb.0: # %entry115; CHECK-SF2-NEXT: movih32 a0, 49440116; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0117; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1118; CHECK-SF2-NEXT: mvc32 a0119; CHECK-SF2-NEXT: rts16120entry:121 %fcmp = fcmp une float %x, -10.0122 ret i1 %fcmp123}124 125define i1 @fcmpRI_X_une(float %x) {126;127; CHECK-SF-LABEL: fcmpRI_X_une:128; CHECK-SF: # %bb.0: # %entry129; CHECK-SF-NEXT: fcmpznes vr0130; CHECK-SF-NEXT: mvc32 a0131; CHECK-SF-NEXT: rts16132;133; CHECK-SF2-LABEL: fcmpRI_X_une:134; CHECK-SF2: # %bb.0: # %entry135; CHECK-SF2-NEXT: fcmpnez.32 vr0136; CHECK-SF2-NEXT: mvc32 a0137; CHECK-SF2-NEXT: rts16138entry:139 %fcmp = fcmp une float %x, 0.0140 ret i1 %fcmp141}142 143 144;ugt145define i1 @fcmpRR_ugt(float %x, float %y) {146;147; CHECK-SF-LABEL: fcmpRR_ugt:148; CHECK-SF: # %bb.0: # %entry149; CHECK-SF-NEXT: fcmphss vr0, vr1150; CHECK-SF-NEXT: mvc32 a0151; CHECK-SF-NEXT: xori32 a0, a0, 1152; CHECK-SF-NEXT: rts16153;154; CHECK-SF2-LABEL: fcmpRR_ugt:155; CHECK-SF2: # %bb.0: # %entry156; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1157; CHECK-SF2-NEXT: mvc32 a0158; CHECK-SF2-NEXT: xori32 a0, a0, 1159; CHECK-SF2-NEXT: rts16160entry:161 %fcmp = fcmp ugt float %y, %x162 ret i1 %fcmp163}164 165define i1 @fcmpRI_ugt(float %x) {166;167; CHECK-SF-LABEL: fcmpRI_ugt:168; CHECK-SF: # %bb.0: # %entry169; CHECK-SF-NEXT: movih32 a0, 49440170; CHECK-SF-NEXT: fmtvrl vr1, a0171; CHECK-SF-NEXT: fcmphss vr1, vr0172; CHECK-SF-NEXT: mvc32 a0173; CHECK-SF-NEXT: xori32 a0, a0, 1174; CHECK-SF-NEXT: rts16175;176; CHECK-SF2-LABEL: fcmpRI_ugt:177; CHECK-SF2: # %bb.0: # %entry178; CHECK-SF2-NEXT: movih32 a0, 49440179; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0180; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0181; CHECK-SF2-NEXT: mvc32 a0182; CHECK-SF2-NEXT: xori32 a0, a0, 1183; CHECK-SF2-NEXT: rts16184entry:185 %fcmp = fcmp ugt float %x, -10.0186 ret i1 %fcmp187}188 189define i1 @fcmpRI_X_ugt(float %x) {190;191; CHECK-SF-LABEL: fcmpRI_X_ugt:192; CHECK-SF: # %bb.0: # %entry193; CHECK-SF-NEXT: fcmpzlss vr0194; CHECK-SF-NEXT: mvc32 a0195; CHECK-SF-NEXT: xori32 a0, a0, 1196; CHECK-SF-NEXT: rts16197;198; CHECK-SF2-LABEL: fcmpRI_X_ugt:199; CHECK-SF2: # %bb.0: # %entry200; CHECK-SF2-NEXT: fcmplsz.32 vr0201; CHECK-SF2-NEXT: mvc32 a0202; CHECK-SF2-NEXT: xori32 a0, a0, 1203; CHECK-SF2-NEXT: rts16204entry:205 %fcmp = fcmp ugt float %x, 0.0206 ret i1 %fcmp207}208 209 210;uge211define i1 @fcmpRR_uge(float %x, float %y) {212;213; CHECK-SF-LABEL: fcmpRR_uge:214; CHECK-SF: # %bb.0: # %entry215; CHECK-SF-NEXT: fcmplts vr1, vr0216; CHECK-SF-NEXT: mvc32 a0217; CHECK-SF-NEXT: xori32 a0, a0, 1218; CHECK-SF-NEXT: rts16219;220; CHECK-SF2-LABEL: fcmpRR_uge:221; CHECK-SF2: # %bb.0: # %entry222; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0223; CHECK-SF2-NEXT: mvc32 a0224; CHECK-SF2-NEXT: xori32 a0, a0, 1225; CHECK-SF2-NEXT: rts16226entry:227 %fcmp = fcmp uge float %y, %x228 ret i1 %fcmp229}230 231define i1 @fcmpRI_uge(float %x) {232;233; CHECK-SF-LABEL: fcmpRI_uge:234; CHECK-SF: # %bb.0: # %entry235; CHECK-SF-NEXT: movih32 a0, 49440236; CHECK-SF-NEXT: fmtvrl vr1, a0237; CHECK-SF-NEXT: fcmplts vr0, vr1238; CHECK-SF-NEXT: mvc32 a0239; CHECK-SF-NEXT: xori32 a0, a0, 1240; CHECK-SF-NEXT: rts16241;242; CHECK-SF2-LABEL: fcmpRI_uge:243; CHECK-SF2: # %bb.0: # %entry244; CHECK-SF2-NEXT: movih32 a0, 49440245; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0246; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1247; CHECK-SF2-NEXT: mvc32 a0248; CHECK-SF2-NEXT: xori32 a0, a0, 1249; CHECK-SF2-NEXT: rts16250entry:251 %fcmp = fcmp uge float %x, -10.0252 ret i1 %fcmp253}254 255define i1 @fcmpRI_X_uge(float %x) {256;257; CHECK-SF-LABEL: fcmpRI_X_uge:258; CHECK-SF: # %bb.0: # %entry259; CHECK-SF-NEXT: fcmpzhss vr0260; CHECK-SF-NEXT: mvcv16 a0261; CHECK-SF-NEXT: xori32 a0, a0, 1262; CHECK-SF-NEXT: rts16263;264; CHECK-SF2-LABEL: fcmpRI_X_uge:265; CHECK-SF2: # %bb.0: # %entry266; CHECK-SF2-NEXT: fcmpltz.32 vr0267; CHECK-SF2-NEXT: mvc32 a0268; CHECK-SF2-NEXT: xori32 a0, a0, 1269; CHECK-SF2-NEXT: rts16270entry:271 %fcmp = fcmp uge float %x, 0.0272 ret i1 %fcmp273}274 275;ult276define i1 @fcmpRR_ult(float %x, float %y) {277;278; CHECK-SF-LABEL: fcmpRR_ult:279; CHECK-SF: # %bb.0: # %entry280; CHECK-SF-NEXT: fcmphss vr1, vr0281; CHECK-SF-NEXT: mvc32 a0282; CHECK-SF-NEXT: xori32 a0, a0, 1283; CHECK-SF-NEXT: rts16284;285; CHECK-SF2-LABEL: fcmpRR_ult:286; CHECK-SF2: # %bb.0: # %entry287; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0288; CHECK-SF2-NEXT: mvc32 a0289; CHECK-SF2-NEXT: xori32 a0, a0, 1290; CHECK-SF2-NEXT: rts16291entry:292 %fcmp = fcmp ult float %y, %x293 ret i1 %fcmp294}295 296define i1 @fcmpRI_ult(float %x) {297;298; CHECK-SF-LABEL: fcmpRI_ult:299; CHECK-SF: # %bb.0: # %entry300; CHECK-SF-NEXT: movih32 a0, 49440301; CHECK-SF-NEXT: fmtvrl vr1, a0302; CHECK-SF-NEXT: fcmphss vr0, vr1303; CHECK-SF-NEXT: mvc32 a0304; CHECK-SF-NEXT: xori32 a0, a0, 1305; CHECK-SF-NEXT: rts16306;307; CHECK-SF2-LABEL: fcmpRI_ult:308; CHECK-SF2: # %bb.0: # %entry309; CHECK-SF2-NEXT: movih32 a0, 49440310; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0311; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1312; CHECK-SF2-NEXT: mvc32 a0313; CHECK-SF2-NEXT: xori32 a0, a0, 1314; CHECK-SF2-NEXT: rts16315entry:316 %fcmp = fcmp ult float %x, -10.0317 ret i1 %fcmp318}319 320define i1 @fcmpRI_X_ult(float %x) {321;322; CHECK-SF-LABEL: fcmpRI_X_ult:323; CHECK-SF: # %bb.0: # %entry324; CHECK-SF-NEXT: fcmpzhss vr0325; CHECK-SF-NEXT: mvc32 a0326; CHECK-SF-NEXT: xori32 a0, a0, 1327; CHECK-SF-NEXT: rts16328;329; CHECK-SF2-LABEL: fcmpRI_X_ult:330; CHECK-SF2: # %bb.0: # %entry331; CHECK-SF2-NEXT: fcmphsz.32 vr0332; CHECK-SF2-NEXT: mvc32 a0333; CHECK-SF2-NEXT: xori32 a0, a0, 1334; CHECK-SF2-NEXT: rts16335entry:336 %fcmp = fcmp ult float %x, 0.0337 ret i1 %fcmp338}339 340 341;ule342define i1 @fcmpRR_ule(float %x, float %y) {343;344; CHECK-SF-LABEL: fcmpRR_ule:345; CHECK-SF: # %bb.0: # %entry346; CHECK-SF-NEXT: fcmplts vr0, vr1347; CHECK-SF-NEXT: mvc32 a0348; CHECK-SF-NEXT: xori32 a0, a0, 1349; CHECK-SF-NEXT: rts16350;351; CHECK-SF2-LABEL: fcmpRR_ule:352; CHECK-SF2: # %bb.0: # %entry353; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1354; CHECK-SF2-NEXT: mvc32 a0355; CHECK-SF2-NEXT: xori32 a0, a0, 1356; CHECK-SF2-NEXT: rts16357entry:358 %fcmp = fcmp ule float %y, %x359 ret i1 %fcmp360}361 362define i1 @fcmpRI_ule(float %x) {363;364; CHECK-SF-LABEL: fcmpRI_ule:365; CHECK-SF: # %bb.0: # %entry366; CHECK-SF-NEXT: movih32 a0, 49440367; CHECK-SF-NEXT: fmtvrl vr1, a0368; CHECK-SF-NEXT: fcmplts vr1, vr0369; CHECK-SF-NEXT: mvc32 a0370; CHECK-SF-NEXT: xori32 a0, a0, 1371; CHECK-SF-NEXT: rts16372;373; CHECK-SF2-LABEL: fcmpRI_ule:374; CHECK-SF2: # %bb.0: # %entry375; CHECK-SF2-NEXT: movih32 a0, 49440376; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0377; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0378; CHECK-SF2-NEXT: mvc32 a0379; CHECK-SF2-NEXT: xori32 a0, a0, 1380; CHECK-SF2-NEXT: rts16381entry:382 %fcmp = fcmp ule float %x, -10.0383 ret i1 %fcmp384}385 386define i1 @fcmpRI_X_ule(float %x) {387;388; CHECK-SF-LABEL: fcmpRI_X_ule:389; CHECK-SF: # %bb.0: # %entry390; CHECK-SF-NEXT: fcmpzlss vr0391; CHECK-SF-NEXT: mvcv16 a0392; CHECK-SF-NEXT: xori32 a0, a0, 1393; CHECK-SF-NEXT: rts16394;395; CHECK-SF2-LABEL: fcmpRI_X_ule:396; CHECK-SF2: # %bb.0: # %entry397; CHECK-SF2-NEXT: fcmphz.32 vr0398; CHECK-SF2-NEXT: mvc32 a0399; CHECK-SF2-NEXT: xori32 a0, a0, 1400; CHECK-SF2-NEXT: rts16401entry:402 %fcmp = fcmp ule float %x, 0.0403 ret i1 %fcmp404}405 406 407;ogt408define i1 @fcmpRR_ogt(float %x, float %y) {409;410; CHECK-SF-LABEL: fcmpRR_ogt:411; CHECK-SF: # %bb.0: # %entry412; CHECK-SF-NEXT: fcmplts vr0, vr1413; CHECK-SF-NEXT: mvc32 a0414; CHECK-SF-NEXT: rts16415;416; CHECK-SF2-LABEL: fcmpRR_ogt:417; CHECK-SF2: # %bb.0: # %entry418; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1419; CHECK-SF2-NEXT: mvc32 a0420; CHECK-SF2-NEXT: rts16421entry:422 %fcmp = fcmp ogt float %y, %x423 ret i1 %fcmp424}425 426define i1 @fcmpRI_ogt(float %x) {427;428; CHECK-SF-LABEL: fcmpRI_ogt:429; CHECK-SF: # %bb.0: # %entry430; CHECK-SF-NEXT: movih32 a0, 49440431; CHECK-SF-NEXT: fmtvrl vr1, a0432; CHECK-SF-NEXT: fcmplts vr1, vr0433; CHECK-SF-NEXT: mvc32 a0434; CHECK-SF-NEXT: rts16435;436; CHECK-SF2-LABEL: fcmpRI_ogt:437; CHECK-SF2: # %bb.0: # %entry438; CHECK-SF2-NEXT: movih32 a0, 49440439; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0440; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0441; CHECK-SF2-NEXT: mvc32 a0442; CHECK-SF2-NEXT: rts16443entry:444 %fcmp = fcmp ogt float %x, -10.0445 ret i1 %fcmp446}447 448define i1 @fcmpRI_X_ogt(float %x) {449;450; CHECK-SF-LABEL: fcmpRI_X_ogt:451; CHECK-SF: # %bb.0: # %entry452; CHECK-SF-NEXT: fcmpzlss vr0453; CHECK-SF-NEXT: mvcv16 a0454; CHECK-SF-NEXT: rts16455;456; CHECK-SF2-LABEL: fcmpRI_X_ogt:457; CHECK-SF2: # %bb.0: # %entry458; CHECK-SF2-NEXT: fcmphz.32 vr0459; CHECK-SF2-NEXT: mvc32 a0460; CHECK-SF2-NEXT: rts16461entry:462 %fcmp = fcmp ogt float %x, 0.0463 ret i1 %fcmp464}465 466 467;oge468define i1 @fcmpRR_oge(float %x, float %y) {469;470; CHECK-SF-LABEL: fcmpRR_oge:471; CHECK-SF: # %bb.0: # %entry472; CHECK-SF-NEXT: fcmphss vr1, vr0473; CHECK-SF-NEXT: mvc32 a0474; CHECK-SF-NEXT: rts16475;476; CHECK-SF2-LABEL: fcmpRR_oge:477; CHECK-SF2: # %bb.0: # %entry478; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0479; CHECK-SF2-NEXT: mvc32 a0480; CHECK-SF2-NEXT: rts16481entry:482 %fcmp = fcmp oge float %y, %x483 ret i1 %fcmp484}485 486define i1 @fcmpRI_oge(float %x) {487;488; CHECK-SF-LABEL: fcmpRI_oge:489; CHECK-SF: # %bb.0: # %entry490; CHECK-SF-NEXT: movih32 a0, 49440491; CHECK-SF-NEXT: fmtvrl vr1, a0492; CHECK-SF-NEXT: fcmphss vr0, vr1493; CHECK-SF-NEXT: mvc32 a0494; CHECK-SF-NEXT: rts16495;496; CHECK-SF2-LABEL: fcmpRI_oge:497; CHECK-SF2: # %bb.0: # %entry498; CHECK-SF2-NEXT: movih32 a0, 49440499; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0500; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1501; CHECK-SF2-NEXT: mvc32 a0502; CHECK-SF2-NEXT: rts16503entry:504 %fcmp = fcmp oge float %x, -10.0505 ret i1 %fcmp506}507 508define i1 @fcmpRI_X_oge(float %x) {509;510; CHECK-SF-LABEL: fcmpRI_X_oge:511; CHECK-SF: # %bb.0: # %entry512; CHECK-SF-NEXT: fcmpzhss vr0513; CHECK-SF-NEXT: mvc32 a0514; CHECK-SF-NEXT: rts16515;516; CHECK-SF2-LABEL: fcmpRI_X_oge:517; CHECK-SF2: # %bb.0: # %entry518; CHECK-SF2-NEXT: fcmphsz.32 vr0519; CHECK-SF2-NEXT: mvc32 a0520; CHECK-SF2-NEXT: rts16521entry:522 %fcmp = fcmp oge float %x, 0.0523 ret i1 %fcmp524}525 526 527;olt528define i1 @fcmpRR_olt(float %x, float %y) {529;530; CHECK-SF-LABEL: fcmpRR_olt:531; CHECK-SF: # %bb.0: # %entry532; CHECK-SF-NEXT: fcmplts vr1, vr0533; CHECK-SF-NEXT: mvc32 a0534; CHECK-SF-NEXT: rts16535;536; CHECK-SF2-LABEL: fcmpRR_olt:537; CHECK-SF2: # %bb.0: # %entry538; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0539; CHECK-SF2-NEXT: mvc32 a0540; CHECK-SF2-NEXT: rts16541entry:542 %fcmp = fcmp olt float %y, %x543 ret i1 %fcmp544}545 546define i1 @fcmpRI_olt(float %x) {547;548; CHECK-SF-LABEL: fcmpRI_olt:549; CHECK-SF: # %bb.0: # %entry550; CHECK-SF-NEXT: movih32 a0, 49440551; CHECK-SF-NEXT: fmtvrl vr1, a0552; CHECK-SF-NEXT: fcmplts vr0, vr1553; CHECK-SF-NEXT: mvc32 a0554; CHECK-SF-NEXT: rts16555;556; CHECK-SF2-LABEL: fcmpRI_olt:557; CHECK-SF2: # %bb.0: # %entry558; CHECK-SF2-NEXT: movih32 a0, 49440559; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0560; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1561; CHECK-SF2-NEXT: mvc32 a0562; CHECK-SF2-NEXT: rts16563entry:564 %fcmp = fcmp olt float %x, -10.0565 ret i1 %fcmp566}567 568define i1 @fcmpRI_X_olt(float %x) {569;570; CHECK-SF-LABEL: fcmpRI_X_olt:571; CHECK-SF: # %bb.0: # %entry572; CHECK-SF-NEXT: fcmpzhss vr0573; CHECK-SF-NEXT: mvcv16 a0574; CHECK-SF-NEXT: rts16575;576; CHECK-SF2-LABEL: fcmpRI_X_olt:577; CHECK-SF2: # %bb.0: # %entry578; CHECK-SF2-NEXT: fcmpltz.32 vr0579; CHECK-SF2-NEXT: mvc32 a0580; CHECK-SF2-NEXT: rts16581entry:582 %fcmp = fcmp olt float %x, 0.0583 ret i1 %fcmp584}585 586 587;ole588define i1 @fcmpRR_ole(float %x, float %y) {589;590; CHECK-SF-LABEL: fcmpRR_ole:591; CHECK-SF: # %bb.0: # %entry592; CHECK-SF-NEXT: fcmphss vr0, vr1593; CHECK-SF-NEXT: mvc32 a0594; CHECK-SF-NEXT: rts16595;596; CHECK-SF2-LABEL: fcmpRR_ole:597; CHECK-SF2: # %bb.0: # %entry598; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1599; CHECK-SF2-NEXT: mvc32 a0600; CHECK-SF2-NEXT: rts16601entry:602 %fcmp = fcmp ole float %y, %x603 ret i1 %fcmp604}605 606define i1 @fcmpRI_ole(float %x) {607;608; CHECK-SF-LABEL: fcmpRI_ole:609; CHECK-SF: # %bb.0: # %entry610; CHECK-SF-NEXT: movih32 a0, 49440611; CHECK-SF-NEXT: fmtvrl vr1, a0612; CHECK-SF-NEXT: fcmphss vr1, vr0613; CHECK-SF-NEXT: mvc32 a0614; CHECK-SF-NEXT: rts16615;616; CHECK-SF2-LABEL: fcmpRI_ole:617; CHECK-SF2: # %bb.0: # %entry618; CHECK-SF2-NEXT: movih32 a0, 49440619; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0620; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0621; CHECK-SF2-NEXT: mvc32 a0622; CHECK-SF2-NEXT: rts16623entry:624 %fcmp = fcmp ole float %x, -10.0625 ret i1 %fcmp626}627 628define i1 @fcmpRI_X_ole(float %x) {629;630; CHECK-SF-LABEL: fcmpRI_X_ole:631; CHECK-SF: # %bb.0: # %entry632; CHECK-SF-NEXT: fcmpzlss vr0633; CHECK-SF-NEXT: mvc32 a0634; CHECK-SF-NEXT: rts16635;636; CHECK-SF2-LABEL: fcmpRI_X_ole:637; CHECK-SF2: # %bb.0: # %entry638; CHECK-SF2-NEXT: fcmplsz.32 vr0639; CHECK-SF2-NEXT: mvc32 a0640; CHECK-SF2-NEXT: rts16641entry:642 %fcmp = fcmp ole float %x, 0.0643 ret i1 %fcmp644}645 646 647;one648define i1 @fcmpRR_one(float %x, float %y) {649;650; CHECK-SF-LABEL: fcmpRR_one:651; CHECK-SF: # %bb.0: # %entry652; CHECK-SF-NEXT: fcmpuos vr1, vr0653; CHECK-SF-NEXT: mvcv16 a0654; CHECK-SF-NEXT: fcmpnes vr1, vr0655; CHECK-SF-NEXT: mvc32 a1656; CHECK-SF-NEXT: and16 a0, a1657; CHECK-SF-NEXT: rts16658;659; CHECK-SF2-LABEL: fcmpRR_one:660; CHECK-SF2: # %bb.0: # %entry661; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0662; CHECK-SF2-NEXT: mvcv16 a0663; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0664; CHECK-SF2-NEXT: mvc32 a1665; CHECK-SF2-NEXT: and16 a0, a1666; CHECK-SF2-NEXT: rts16667entry:668 %fcmp = fcmp one float %y, %x669 ret i1 %fcmp670}671 672define i1 @fcmpRI_one(float %x) {673;674; CHECK-SF-LABEL: fcmpRI_one:675; CHECK-SF: # %bb.0: # %entry676; CHECK-SF-NEXT: movih32 a0, 49440677; CHECK-SF-NEXT: fmtvrl vr1, a0678; CHECK-SF-NEXT: fcmpnes vr0, vr1679; CHECK-SF-NEXT: mvc32 a0680; CHECK-SF-NEXT: fcmpuos vr0, vr0681; CHECK-SF-NEXT: mvcv16 a1682; CHECK-SF-NEXT: and16 a0, a1683; CHECK-SF-NEXT: rts16684;685; CHECK-SF2-LABEL: fcmpRI_one:686; CHECK-SF2: # %bb.0: # %entry687; CHECK-SF2-NEXT: movih32 a0, 49440688; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0689; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1690; CHECK-SF2-NEXT: mvc32 a0691; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0692; CHECK-SF2-NEXT: mvcv16 a1693; CHECK-SF2-NEXT: and16 a0, a1694; CHECK-SF2-NEXT: rts16695entry:696 %fcmp = fcmp one float %x, -10.0697 ret i1 %fcmp698}699 700define i1 @fcmpRI_X_one(float %x) {701;702; CHECK-SF-LABEL: fcmpRI_X_one:703; CHECK-SF: # %bb.0: # %entry704; CHECK-SF-NEXT: fcmpuos vr0, vr0705; CHECK-SF-NEXT: mvcv16 a0706; CHECK-SF-NEXT: fcmpznes vr0707; CHECK-SF-NEXT: mvc32 a1708; CHECK-SF-NEXT: and16 a0, a1709; CHECK-SF-NEXT: rts16710;711; CHECK-SF2-LABEL: fcmpRI_X_one:712; CHECK-SF2: # %bb.0: # %entry713; CHECK-SF2-NEXT: movi16 a0, 0714; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0715; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1716; CHECK-SF2-NEXT: mvc32 a0717; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0718; CHECK-SF2-NEXT: mvcv16 a1719; CHECK-SF2-NEXT: and16 a0, a1720; CHECK-SF2-NEXT: rts16721entry:722 %fcmp = fcmp one float %x, 0.0723 ret i1 %fcmp724}725 726 727;oeq728define i1 @fcmpRR_oeq(float %x, float %y) {729;730; CHECK-SF-LABEL: fcmpRR_oeq:731; CHECK-SF: # %bb.0: # %entry732; CHECK-SF-NEXT: fcmpnes vr1, vr0733; CHECK-SF-NEXT: mvcv16 a0734; CHECK-SF-NEXT: rts16735;736; CHECK-SF2-LABEL: fcmpRR_oeq:737; CHECK-SF2: # %bb.0: # %entry738; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0739; CHECK-SF2-NEXT: mvcv16 a0740; CHECK-SF2-NEXT: rts16741entry:742 %fcmp = fcmp oeq float %y, %x743 ret i1 %fcmp744}745 746define i1 @fcmpRI_oeq(float %x) {747;748; CHECK-SF-LABEL: fcmpRI_oeq:749; CHECK-SF: # %bb.0: # %entry750; CHECK-SF-NEXT: movih32 a0, 49440751; CHECK-SF-NEXT: fmtvrl vr1, a0752; CHECK-SF-NEXT: fcmpnes vr0, vr1753; CHECK-SF-NEXT: mvcv16 a0754; CHECK-SF-NEXT: rts16755;756; CHECK-SF2-LABEL: fcmpRI_oeq:757; CHECK-SF2: # %bb.0: # %entry758; CHECK-SF2-NEXT: movih32 a0, 49440759; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0760; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1761; CHECK-SF2-NEXT: mvcv16 a0762; CHECK-SF2-NEXT: rts16763entry:764 %fcmp = fcmp oeq float %x, -10.0765 ret i1 %fcmp766}767 768define i1 @fcmpRI_X_oeq(float %x) {769;770; CHECK-SF-LABEL: fcmpRI_X_oeq:771; CHECK-SF: # %bb.0: # %entry772; CHECK-SF-NEXT: fcmpznes vr0773; CHECK-SF-NEXT: mvcv16 a0774; CHECK-SF-NEXT: rts16775;776; CHECK-SF2-LABEL: fcmpRI_X_oeq:777; CHECK-SF2: # %bb.0: # %entry778; CHECK-SF2-NEXT: fcmpnez.32 vr0779; CHECK-SF2-NEXT: mvcv16 a0780; CHECK-SF2-NEXT: rts16781entry:782 %fcmp = fcmp oeq float %x, 0.0783 ret i1 %fcmp784}785 786 787;ord788define i1 @fcmpRR_ord(float %x, float %y) {789;790; CHECK-SF-LABEL: fcmpRR_ord:791; CHECK-SF: # %bb.0: # %entry792; CHECK-SF-NEXT: fcmpuos vr1, vr0793; CHECK-SF-NEXT: mvcv16 a0794; CHECK-SF-NEXT: rts16795;796; CHECK-SF2-LABEL: fcmpRR_ord:797; CHECK-SF2: # %bb.0: # %entry798; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0799; CHECK-SF2-NEXT: mvcv16 a0800; CHECK-SF2-NEXT: rts16801entry:802 %fcmp = fcmp ord float %y, %x803 ret i1 %fcmp804}805 806define i1 @fcmpRI_ord(float %x) {807;808; CHECK-SF-LABEL: fcmpRI_ord:809; CHECK-SF: # %bb.0: # %entry810; CHECK-SF-NEXT: fcmpuos vr0, vr0811; CHECK-SF-NEXT: mvcv16 a0812; CHECK-SF-NEXT: rts16813;814; CHECK-SF2-LABEL: fcmpRI_ord:815; CHECK-SF2: # %bb.0: # %entry816; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0817; CHECK-SF2-NEXT: mvcv16 a0818; CHECK-SF2-NEXT: rts16819entry:820 %fcmp = fcmp ord float %x, -10.0821 ret i1 %fcmp822}823 824define i1 @fcmpRI_X_ord(float %x) {825;826; CHECK-SF-LABEL: fcmpRI_X_ord:827; CHECK-SF: # %bb.0: # %entry828; CHECK-SF-NEXT: fcmpuos vr0, vr0829; CHECK-SF-NEXT: mvcv16 a0830; CHECK-SF-NEXT: rts16831;832; CHECK-SF2-LABEL: fcmpRI_X_ord:833; CHECK-SF2: # %bb.0: # %entry834; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0835; CHECK-SF2-NEXT: mvcv16 a0836; CHECK-SF2-NEXT: rts16837entry:838 %fcmp = fcmp ord float %x, 0.0839 ret i1 %fcmp840}841 842 843;uno844define i1 @fcmpRR_uno(float %x, float %y) {845;846; CHECK-SF-LABEL: fcmpRR_uno:847; CHECK-SF: # %bb.0: # %entry848; CHECK-SF-NEXT: fcmpuos vr1, vr0849; CHECK-SF-NEXT: mvc32 a0850; CHECK-SF-NEXT: rts16851;852; CHECK-SF2-LABEL: fcmpRR_uno:853; CHECK-SF2: # %bb.0: # %entry854; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0855; CHECK-SF2-NEXT: mvc32 a0856; CHECK-SF2-NEXT: rts16857entry:858 %fcmp = fcmp uno float %y, %x859 ret i1 %fcmp860}861 862define i1 @fcmpRI_uno(float %x) {863;864; CHECK-SF-LABEL: fcmpRI_uno:865; CHECK-SF: # %bb.0: # %entry866; CHECK-SF-NEXT: fcmpuos vr0, vr0867; CHECK-SF-NEXT: mvc32 a0868; CHECK-SF-NEXT: rts16869;870; CHECK-SF2-LABEL: fcmpRI_uno:871; CHECK-SF2: # %bb.0: # %entry872; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0873; CHECK-SF2-NEXT: mvc32 a0874; CHECK-SF2-NEXT: rts16875entry:876 %fcmp = fcmp uno float %x, -10.0877 ret i1 %fcmp878}879 880define i1 @fcmpRI_X_uno(float %x) {881;882; CHECK-SF-LABEL: fcmpRI_X_uno:883; CHECK-SF: # %bb.0: # %entry884; CHECK-SF-NEXT: fcmpuos vr0, vr0885; CHECK-SF-NEXT: mvc32 a0886; CHECK-SF-NEXT: rts16887;888; CHECK-SF2-LABEL: fcmpRI_X_uno:889; CHECK-SF2: # %bb.0: # %entry890; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0891; CHECK-SF2-NEXT: mvc32 a0892; CHECK-SF2-NEXT: rts16893entry:894 %fcmp = fcmp uno float %x, 0.0895 ret i1 %fcmp896}897