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1; RUN: opt -S -dxil-op-lower -dxil-translate-metadata -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s2 3; This test make sure LLVM metadata is being translated into DXIL.4 5 6; CHECK: define i32 @test_branch(i32 %X)7; CHECK-NOT: hlsl.controlflow.hint8; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_BRANCH:![0-9]+]]9define i32 @test_branch(i32 %X) {10entry:11 %X.addr = alloca i32, align 412 %resp = alloca i32, align 413 store i32 %X, ptr %X.addr, align 414 %0 = load i32, ptr %X.addr, align 415 %cmp = icmp sgt i32 %0, 016 br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !017 18if.then: ; preds = %entry19 %1 = load i32, ptr %X.addr, align 420 %sub = sub nsw i32 0, %121 store i32 %sub, ptr %resp, align 422 br label %if.end23 24if.else: ; preds = %entry25 %2 = load i32, ptr %X.addr, align 426 %mul = mul nsw i32 %2, 227 store i32 %mul, ptr %resp, align 428 br label %if.end29 30if.end: ; preds = %if.else, %if.then31 %3 = load i32, ptr %resp, align 432 ret i32 %333}34 35 36; CHECK: define i32 @test_flatten(i32 %X)37; CHECK-NOT: hlsl.controlflow.hint38; CHECK: br i1 %cmp, label %if.then, label %if.else, !dx.controlflow.hints [[HINT_FLATTEN:![0-9]+]]39define i32 @test_flatten(i32 %X) {40entry:41 %X.addr = alloca i32, align 442 %resp = alloca i32, align 443 store i32 %X, ptr %X.addr, align 444 %0 = load i32, ptr %X.addr, align 445 %cmp = icmp sgt i32 %0, 046 br i1 %cmp, label %if.then, label %if.else, !hlsl.controlflow.hint !147 48if.then: ; preds = %entry49 %1 = load i32, ptr %X.addr, align 450 %sub = sub nsw i32 0, %151 store i32 %sub, ptr %resp, align 452 br label %if.end53 54if.else: ; preds = %entry55 %2 = load i32, ptr %X.addr, align 456 %mul = mul nsw i32 %2, 257 store i32 %mul, ptr %resp, align 458 br label %if.end59 60if.end: ; preds = %if.else, %if.then61 %3 = load i32, ptr %resp, align 462 ret i32 %363}64 65 66; CHECK: define i32 @test_no_attr(i32 %X)67; CHECK-NOT: hlsl.controlflow.hint68; CHECK-NOT: !dx.controlflow.hints69define i32 @test_no_attr(i32 %X) {70entry:71 %X.addr = alloca i32, align 472 %resp = alloca i32, align 473 store i32 %X, ptr %X.addr, align 474 %0 = load i32, ptr %X.addr, align 475 %cmp = icmp sgt i32 %0, 076 br i1 %cmp, label %if.then, label %if.else77 78if.then: ; preds = %entry79 %1 = load i32, ptr %X.addr, align 480 %sub = sub nsw i32 0, %181 store i32 %sub, ptr %resp, align 482 br label %if.end83 84if.else: ; preds = %entry85 %2 = load i32, ptr %X.addr, align 486 %mul = mul nsw i32 %2, 287 store i32 %mul, ptr %resp, align 488 br label %if.end89 90if.end: ; preds = %if.else, %if.then91 %3 = load i32, ptr %resp, align 492 ret i32 %393}94 95; CHECK: define i32 @flatten_switch(i32 %X)96; CHECK-NOT: hlsl.controlflow.hint97; CHECK: switch i32 %0, label %sw.epilog [98; CHECK-NEXT: i32 0, label %sw.bb99; CHECK-NEXT: i32 1, label %sw.bb1100; CHECK-NEXT: i32 2, label %sw.bb2101; CHECK-NEXT: ], !dx.controlflow.hints [[HINT_FLATTEN]]102define i32 @flatten_switch(i32 %X) #0 {103entry:104 %X.addr = alloca i32, align 4105 %resp = alloca i32, align 4106 store i32 %X, ptr %X.addr, align 4107 %0 = load i32, ptr %X.addr, align 4108 switch i32 %0, label %sw.epilog [109 i32 0, label %sw.bb110 i32 1, label %sw.bb1111 i32 2, label %sw.bb2112 ], !hlsl.controlflow.hint !1113 114sw.bb: ; preds = %entry115 %1 = load i32, ptr %X.addr, align 4116 %sub = sub nsw i32 0, %1117 store i32 %sub, ptr %resp, align 4118 br label %sw.epilog119 120sw.bb1: ; preds = %entry121 %2 = load i32, ptr %X.addr, align 4122 %3 = load i32, ptr %X.addr, align 4123 %add = add nsw i32 %2, %3124 store i32 %add, ptr %resp, align 4125 br label %sw.epilog126 127sw.bb2: ; preds = %entry128 %4 = load i32, ptr %X.addr, align 4129 %5 = load i32, ptr %X.addr, align 4130 %mul = mul nsw i32 %4, %5131 store i32 %mul, ptr %resp, align 4132 br label %sw.epilog133 134sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb135 %6 = load i32, ptr %resp, align 4136 ret i32 %6137}138 139 140; CHECK: define i32 @branch_switch(i32 %X)141; CHECK-NOT: hlsl.controlflow.hint142; CHECK: switch i32 %0, label %sw.epilog [143; CHECK-NEXT: i32 0, label %sw.bb144; CHECK-NEXT: i32 1, label %sw.bb1145; CHECK-NEXT: i32 2, label %sw.bb2146; CHECK-NEXT: ], !dx.controlflow.hints [[HINT_BRANCH]]147define i32 @branch_switch(i32 %X) #0 {148entry:149 %X.addr = alloca i32, align 4150 %resp = alloca i32, align 4151 store i32 %X, ptr %X.addr, align 4152 %0 = load i32, ptr %X.addr, align 4153 switch i32 %0, label %sw.epilog [154 i32 0, label %sw.bb155 i32 1, label %sw.bb1156 i32 2, label %sw.bb2157 ], !hlsl.controlflow.hint !0158 159sw.bb: ; preds = %entry160 %1 = load i32, ptr %X.addr, align 4161 %sub = sub nsw i32 0, %1162 store i32 %sub, ptr %resp, align 4163 br label %sw.epilog164 165sw.bb1: ; preds = %entry166 %2 = load i32, ptr %X.addr, align 4167 %3 = load i32, ptr %X.addr, align 4168 %add = add nsw i32 %2, %3169 store i32 %add, ptr %resp, align 4170 br label %sw.epilog171 172sw.bb2: ; preds = %entry173 %4 = load i32, ptr %X.addr, align 4174 %5 = load i32, ptr %X.addr, align 4175 %mul = mul nsw i32 %4, %5176 store i32 %mul, ptr %resp, align 4177 br label %sw.epilog178 179sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb180 %6 = load i32, ptr %resp, align 4181 ret i32 %6182}183 184 185; CHECK: define i32 @no_attr_switch(i32 %X)186; CHECK-NOT: hlsl.controlflow.hint187; CHECK-NOT: !dx.controlflow.hints188define i32 @no_attr_switch(i32 %X) #0 {189entry:190 %X.addr = alloca i32, align 4191 %resp = alloca i32, align 4192 store i32 %X, ptr %X.addr, align 4193 %0 = load i32, ptr %X.addr, align 4194 switch i32 %0, label %sw.epilog [195 i32 0, label %sw.bb196 i32 1, label %sw.bb1197 i32 2, label %sw.bb2198 ]199 200sw.bb: ; preds = %entry201 %1 = load i32, ptr %X.addr, align 4202 %sub = sub nsw i32 0, %1203 store i32 %sub, ptr %resp, align 4204 br label %sw.epilog205 206sw.bb1: ; preds = %entry207 %2 = load i32, ptr %X.addr, align 4208 %3 = load i32, ptr %X.addr, align 4209 %add = add nsw i32 %2, %3210 store i32 %add, ptr %resp, align 4211 br label %sw.epilog212 213sw.bb2: ; preds = %entry214 %4 = load i32, ptr %X.addr, align 4215 %5 = load i32, ptr %X.addr, align 4216 %mul = mul nsw i32 %4, %5217 store i32 %mul, ptr %resp, align 4218 br label %sw.epilog219 220sw.epilog: ; preds = %entry, %sw.bb2, %sw.bb1, %sw.bb221 %6 = load i32, ptr %resp, align 4222 ret i32 %6223}224 225; CHECK-NOT: hlsl.controlflow.hint226; CHECK: [[HINT_BRANCH]] = !{!"dx.controlflow.hints", i32 1}227; CHECK: [[HINT_FLATTEN]] = !{!"dx.controlflow.hints", i32 2}228!0 = !{!"hlsl.controlflow.hint", i32 1}229!1 = !{!"hlsl.controlflow.hint", i32 2}230