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1; RUN: opt -mtriple=dxil-pc-shadermodel6.2-compute -S -dxil-intrinsic-expansion %s | FileCheck %s --check-prefixes=CHECK,CHECK622; RUN: opt -mtriple=dxil-pc-shadermodel6.3-compute -S -dxil-intrinsic-expansion %s | FileCheck %s --check-prefixes=CHECK,CHECK633 4define void @loadi64(i32 %index) {5 ; check the handle from binding is unchanged6 ; CHECK: [[B:%.*]] = call target("dx.Rawbuffer", i64, 1, 0, 0)7 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_i64_1_0_0t(8 ; CHECK-SAME: i32 0, i32 1, i32 1, i32 0, ptr null)9 %buffer = call target("dx.Rawbuffer", i64, 1, 0, 0)10 @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_i64_1_0_0t(11 i32 0, i32 1, i32 1, i32 0, ptr null)12 13 ; check we don't modify the code in sm6.3 or later14 ; CHECK63: [[L0:%.*]] = call { i64, i1 } @llvm.dx.resource.load.rawbuffer15 ; CHECK63-SAME: target("dx.Rawbuffer", i64, 1, 0, 0) [[B]], i32 %index, i32 0)16 17 ; check we load an <2 x i32> instead of a i6418 ; CHECK62-NOT: call {i64, i1} @llvm.dx.resource.load.rawbuffer19 ; CHECK62: [[L0:%.*]] = call { <2 x i32>, i1 }20 ; CHECK62-SAME: @llvm.dx.resource.load.rawbuffer.v2i32.tdx.Rawbuffer_i64_1_0_0t(21 ; CHECK62-SAME: target("dx.Rawbuffer", i64, 1, 0, 0) [[B]], i32 %index, i32 0) 22 %load0 = call {i64, i1} @llvm.dx.resource.load.rawbuffer(23 target("dx.Rawbuffer", i64, 1, 0, 0) %buffer, i32 %index, i32 0)24 25 ; CHECK63: extractvalue { i64, i1 } [[L0]], 026 27 ; check we extract the two i32 and construct a i6428 ; CHECK62: [[D0:%.*]] = extractvalue { <2 x i32>, i1 } [[L0]], 029 ; CHECK62: [[Lo:%.*]] = extractelement <2 x i32> [[D0]], i32 030 ; CHECK62: [[Hi:%.*]] = extractelement <2 x i32> [[D0]], i32 131 ; CHECK62: [[ZLo1:%.*]] = zext i32 [[Lo]] to i6432 ; CHECK62: [[ZHi1:%.*]] = zext i32 [[Hi]] to i6433 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi1]], 3234 ; CHECK62: [[B:%.*]] = or i64 [[ZLo1]], [[A]]35 ; CHECK62-NOT: extractvalue { i64, i1 }36 %data0 = extractvalue {i64, i1} %load0, 037 ret void38}39 40define void @loadv2i64(i32 %index) {41 ; check the handle from binding is unchanged42 ; CHECK: [[B:%.*]] = call target("dx.Rawbuffer", <2 x i64>, 1, 0, 0)43 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_v2i64_1_0_0t(44 ; CHECK-SAME: i32 0, i32 1, i32 1, i32 0, ptr null)45 %buffer = call target("dx.Rawbuffer", <2 x i64>, 1, 0, 0)46 @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_v2i64_1_0_0t(47 i32 0, i32 1, i32 1, i32 0, ptr null)48 49 ; check we don't modify the code in sm6.3 or later50 ; CHECK63: [[L0:%.*]] = call { <2 x i64>, i1 } @llvm.dx.resource.load.rawbuffer51 ; CHECK63-SAME: target("dx.Rawbuffer", <2 x i64>, 1, 0, 0) [[B]], i32 %index, i32 0)52 53 ; check we load an <4 x i32> instead of a i64254 ; CHECK62: [[L0:%.*]] = call { <4 x i32>, i1 }55 ; CHECK62-SAME: @llvm.dx.resource.load.rawbuffer.v4i32.tdx.Rawbuffer_v2i64_1_0_0t(56 ; CHECK62-SAME: target("dx.Rawbuffer", <2 x i64>, 1, 0, 0) [[B]], i32 %index, i32 0)57 %load0 = call { <2 x i64>, i1 } @llvm.dx.resource.load.rawbuffer(58 target("dx.Rawbuffer", <2 x i64>, 1, 0, 0) %buffer, i32 %index, i32 0)59 60 ; CHECK63: extractvalue { <2 x i64>, i1 } [[L0]], 061 62 ; check we extract the 4 i32 and construct a <2 x i64>63 ; CHECK62: [[D0:%.*]] = extractvalue { <4 x i32>, i1 } [[L0]], 064 ; CHECK62: [[Lo1:%.*]] = extractelement <4 x i32> [[D0]], i32 065 ; CHECK62: [[Hi1:%.*]] = extractelement <4 x i32> [[D0]], i32 166 ; CHECK62: [[Lo2:%.*]] = extractelement <4 x i32> [[D0]], i32 267 ; CHECK62: [[Hi2:%.*]] = extractelement <4 x i32> [[D0]], i32 368 ; CHECK62: [[ZLo1:%.*]] = zext i32 [[Lo1]] to i6469 ; CHECK62: [[ZHi1:%.*]] = zext i32 [[Hi1]] to i6470 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi1]], 3271 ; CHECK62: [[B:%.*]] = or i64 [[ZLo1]], [[A]]72 ; CHECK62: [[Vec:%.*]] = insertelement <2 x i64> poison, i64 [[B]], i32 073 ; CHECK62: [[ZLo2:%.*]] = zext i32 [[Lo2]] to i6474 ; CHECK62: [[ZHi2:%.*]] = zext i32 [[Hi2]] to i6475 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi2]], 3276 ; CHECK62: [[B:%.*]] = or i64 [[ZLo2]], [[A]]77 ; CHECK62: [[Vec2:%.*]] = insertelement <2 x i64> [[Vec]], i64 [[B]], i32 178 ; CHECK62-NOT: extractvalue { <2 x i64>, i1 }79 %data0 = extractvalue { <2 x i64>, i1 } %load0, 080 ret void81}82 83; show we properly handle extracting the check bit84define void @loadi64WithCheckBit(i32 %index) {85 ; check the handle from binding is unchanged86 ; CHECK: [[B:%.*]] = call target("dx.Rawbuffer", i64, 1, 0, 0)87 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_i64_1_0_0t(88 ; CHECK-SAME: i32 0, i32 1, i32 1, i32 0, ptr null)89 %buffer = call target("dx.Rawbuffer", i64, 1, 0, 0)90 @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_i64_1_0_0t(91 i32 0, i32 1, i32 1, i32 0, ptr null)92 93 ; check we don't modify the code in sm6.3 or later94 ; CHECK63: [[L0:%.*]] = call { i64, i1 } @llvm.dx.resource.load.rawbuffer95 ; CHECK63-SAME: target("dx.Rawbuffer", i64, 1, 0, 0) [[B]], i32 %index, i32 0)96 97 ; check we load an <2 x i32> instead of a i6498 ; CHECK62-NOT: call {i64, i1} @llvm.dx.resource.load.rawbuffer99 ; CHECK62: [[L0:%.*]] = call { <2 x i32>, i1 }100 ; CHECK62-SAME: @llvm.dx.resource.load.rawbuffer.v2i32.tdx.Rawbuffer_i64_1_0_0t(101 ; CHECK62-SAME: target("dx.Rawbuffer", i64, 1, 0, 0) [[B]], i32 %index, i32 0) 102 %load0 = call {i64, i1} @llvm.dx.resource.load.rawbuffer(103 target("dx.Rawbuffer", i64, 1, 0, 0) %buffer, i32 %index, i32 0)104 105 ; CHECK63: extractvalue { i64, i1 } [[L0]], 0106 ; CHECK63: extractvalue { i64, i1 } [[L0]], 1107 108 ; check we extract the two i32 and construct a i64109 ; CHECK62: [[D0:%.*]] = extractvalue { <2 x i32>, i1 } [[L0]], 0110 ; CHECK62: [[Lo:%.*]] = extractelement <2 x i32> [[D0]], i32 0111 ; CHECK62: [[Hi:%.*]] = extractelement <2 x i32> [[D0]], i32 1112 ; CHECK62: [[ZLo1:%.*]] = zext i32 [[Lo]] to i64113 ; CHECK62: [[ZHi1:%.*]] = zext i32 [[Hi]] to i64114 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi1]], 32115 ; CHECK62: [[B:%.*]] = or i64 [[ZLo1]], [[A]]116 %data0 = extractvalue {i64, i1} %load0, 0117 ; CHECK62: extractvalue { <2 x i32>, i1 } [[L0]], 1118 ; CHECK62-NOT: extractvalue { i64, i1 }119 %cb = extractvalue {i64, i1} %load0, 1120 ret void121}122 123; Raw Buffer Load allows for i64_t3 and i64_t4 to be loaded124; In SM6.2 and below, two loads will be performed.125; Show we and the checkbits together126 127define void @loadv3i64(i32 %index) {128 ; check the handle from binding is unchanged129 ; CHECK: [[Buf:%.*]] = call target("dx.Rawbuffer", <3 x i64>, 0, 0)130 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_v3i64_0_0t(131 ; CHECK-SAME: i32 0, i32 0, i32 1, i32 0, ptr null)132 %buffer = call target("dx.Rawbuffer", <3 x i64>, 0, 0)133 @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_v3i64_0_0t(134 i32 0, i32 0, i32 1, i32 0, ptr null)135 136 ; check we don't modify the code in sm6.3 or later137 ; CHECK63: [[L0:%.*]] = call { <3 x i64>, i1 } @llvm.dx.resource.load.rawbuffer138 ; CHECK63-SAME: target("dx.Rawbuffer", <3 x i64>, 0, 0) [[B]], i32 %index, i32 0)139 140 ; check we perform two loads141 ; and do 6 extracts and construct 3 i64s142 ; CHECK62-NOT: call {<3 x i64>, i1} @llvm.dx.resource.load.rawbuffer143 ; CHECK62: [[L0:%.*]] = call { <4 x i32>, i1 }144 ; CHECK62-SAME: @llvm.dx.resource.load.rawbuffer.v4i32.tdx.Rawbuffer_v3i64_0_0t(145 ; CHECK62-SAME: target("dx.Rawbuffer", <3 x i64>, 0, 0) [[Buf]], i32 %index, i32 0)146 147 ; CHECK62: [[D0:%.*]] = extractvalue { <4 x i32>, i1 } [[L0]], 0148 ; CHECK62: [[Lo1:%.*]] = extractelement <4 x i32> [[D0]], i32 0149 ; CHECK62: [[Hi1:%.*]] = extractelement <4 x i32> [[D0]], i32 1150 ; CHECK62: [[Lo2:%.*]] = extractelement <4 x i32> [[D0]], i32 2151 ; CHECK62: [[Hi2:%.*]] = extractelement <4 x i32> [[D0]], i32 3152 ; CHECK62: [[ZLo1:%.*]] = zext i32 [[Lo1]] to i64153 ; CHECK62: [[ZHi1:%.*]] = zext i32 [[Hi1]] to i64154 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi1]], 32155 ; CHECK62: [[B:%.*]] = or i64 [[ZLo1]], [[A]]156 ; CHECK62: [[Vec1:%.*]] = insertelement <3 x i64> poison, i64 [[B]], i32 0157 ; CHECK62: [[ZLo2:%.*]] = zext i32 [[Lo2]] to i64158 ; CHECK62: [[ZHi2:%.*]] = zext i32 [[Hi2]] to i64159 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi2]], 32160 ; CHECK62: [[B:%.*]] = or i64 [[ZLo2]], [[A]]161 ; CHECK62: [[Vec2:%.*]] = insertelement <3 x i64> [[Vec1]], i64 [[B]], i32 1162 163 ; 2nd load164 ; CHECK62: [[L2:%.*]] = call { <2 x i32>, i1 }165 ; CHECK62-SAME: @llvm.dx.resource.load.rawbuffer.v2i32.tdx.Rawbuffer_v3i64_0_0t(166 ; CHECK62-SAME: target("dx.Rawbuffer", <3 x i64>, 0, 0) [[Buf]], i32 %index, i32 16)167 168 ; CHECK62: [[D2:%.*]] = extractvalue { <2 x i32>, i1 } [[L2]], 0169 ; CHECK62: [[Lo3:%.*]] = extractelement <2 x i32> [[D2]], i32 0170 ; CHECK62: [[Hi3:%.*]] = extractelement <2 x i32> [[D2]], i32 1171 ; CHECK62: [[ZLo3:%.*]] = zext i32 [[Lo3]] to i64172 ; CHECK62: [[ZHi3:%.*]] = zext i32 [[Hi3]] to i64173 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi3]], 32174 ; CHECK62: [[B:%.*]] = or i64 [[ZLo3]], [[A]]175 ; CHECK62: [[Vec3:%.*]] = insertelement <3 x i64> [[Vec2]], i64 [[B]], i32 2176 %load0 = call {<3 x i64>, i1} @llvm.dx.resource.load.rawbuffer(177 target("dx.Rawbuffer", <3 x i64>, 0, 0) %buffer, i32 %index, i32 0)178 179 ; CHECK63: extractvalue { <3 x i64>, i1 } [[L0]], 0180 ; CHECK63: extractvalue { <3 x i64>, i1 } [[L0]], 1181 182 ; CHECK62-NOT: extractvalue {<3 x i64>, i1 }183 %data0 = extractvalue {<3 x i64>, i1} %load0, 0184 ; check we extract checkbit from both loads and and them together185 ; CHECK62: [[B1:%.*]] = extractvalue { <4 x i32>, i1 } [[L0]], 1186 ; CHECK62: [[B2:%.*]] = extractvalue { <2 x i32>, i1 } [[L2]], 1187 ; CHECK62: and i1 [[B1]], [[B2]]188 %cb = extractvalue {<3 x i64>, i1} %load0, 1189 ret void190}191 192define void @loadv4i64(i32 %index) {193 ; check the handle from binding is unchanged194 ; CHECK62: [[Buf:%.*]] = call target("dx.Rawbuffer", <4 x i64>, 0, 0)195 ; CHECK62-SAME: @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_v4i64_0_0t(196 ; CHECK62-SAME: i32 0, i32 0, i32 1, i32 0, ptr null)197 %buffer = call target("dx.Rawbuffer", <4 x i64>, 0, 0)198 @llvm.dx.resource.handlefrombinding.tdx.Rawbuffer_v4i64_0_0t(199 i32 0, i32 0, i32 1, i32 0, ptr null)200 201 ; check we don't modify the code in sm6.3 or later202 ; CHECK63: [[L0:%.*]] = call { <4 x i64>, i1 } @llvm.dx.resource.load.rawbuffer203 ; CHECK63-SAME: target("dx.Rawbuffer", <4 x i64>, 0, 0) [[B]], i32 %index, i32 0)204 205 ; check we perform two loads206 ; and do 8 extracts and construct 4 i64s207 ; CHECK62-NOT: call {<4 x i64>, i1} @llvm.dx.resource.load.rawbuffer208 ; CHECK62: [[L0:%.*]] = call { <4 x i32>, i1 }209 ; CHECK62-SAME: @llvm.dx.resource.load.rawbuffer.v4i32.tdx.Rawbuffer_v4i64_0_0t(210 ; CHECK62-SAME: target("dx.Rawbuffer", <4 x i64>, 0, 0) [[Buf]], i32 %index, i32 0)211 212 ; CHECK62: [[D0:%.*]] = extractvalue { <4 x i32>, i1 } [[L0]], 0213 ; CHECK62: [[Lo1:%.*]] = extractelement <4 x i32> [[D0]], i32 0214 ; CHECK62: [[Hi1:%.*]] = extractelement <4 x i32> [[D0]], i32 1215 ; CHECK62: [[Lo2:%.*]] = extractelement <4 x i32> [[D0]], i32 2216 ; CHECK62: [[Hi2:%.*]] = extractelement <4 x i32> [[D0]], i32 3217 ; CHECK62: [[ZLo1:%.*]] = zext i32 [[Lo1]] to i64218 ; CHECK62: [[ZHi1:%.*]] = zext i32 [[Hi1]] to i64219 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi1]], 32220 ; CHECK62: [[B:%.*]] = or i64 [[ZLo1]], [[A]]221 ; CHECK62: [[Vec1:%.*]] = insertelement <4 x i64> poison, i64 [[B]], i32 0222 ; CHECK62: [[ZLo2:%.*]] = zext i32 [[Lo2]] to i64223 ; CHECK62: [[ZHi2:%.*]] = zext i32 [[Hi2]] to i64224 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi2]], 32225 ; CHECK62: [[B:%.*]] = or i64 [[ZLo2]], [[A]]226 ; CHECK62: [[Vec2:%.*]] = insertelement <4 x i64> [[Vec1]], i64 [[B]], i32 1227 228 ; 2nd load229 ; CHECK62: [[L2:%.*]] = call { <4 x i32>, i1 }230 ; CHECK62-SAME: @llvm.dx.resource.load.rawbuffer.v4i32.tdx.Rawbuffer_v4i64_0_0t(231 ; CHECK62-SAME: target("dx.Rawbuffer", <4 x i64>, 0, 0) [[Buf]], i32 %index, i32 16)232 233 ; CHECK62: [[D2:%.*]] = extractvalue { <4 x i32>, i1 } [[L2]], 0234 ; CHECK62: [[Lo3:%.*]] = extractelement <4 x i32> [[D2]], i32 0235 ; CHECK62: [[Hi3:%.*]] = extractelement <4 x i32> [[D2]], i32 1236 ; CHECK62: [[Lo4:%.*]] = extractelement <4 x i32> [[D2]], i32 2237 ; CHECK62: [[Hi4:%.*]] = extractelement <4 x i32> [[D2]], i32 3238 ; CHECK62: [[ZLo3:%.*]] = zext i32 [[Lo3]] to i64239 ; CHECK62: [[ZHi3:%.*]] = zext i32 [[Hi3]] to i64240 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi3]], 32241 ; CHECK62: [[B:%.*]] = or i64 [[ZLo3]], [[A]]242 ; CHECK62: [[Vec3:%.*]] = insertelement <4 x i64> [[Vec2]], i64 [[B]], i32 2243 ; CHECK62: [[ZLo4:%.*]] = zext i32 [[Lo4]] to i64244 ; CHECK62: [[ZHi4:%.*]] = zext i32 [[Hi4]] to i64245 ; CHECK62: [[A:%.*]] = shl i64 [[ZHi4]], 32246 ; CHECK62: [[B:%.*]] = or i64 [[ZLo4]], [[A]]247 ; CHECK62: [[Vec4:%.*]] = insertelement <4 x i64> [[Vec3]], i64 [[B]], i32 3248 %load0 = call {<4 x i64>, i1} @llvm.dx.resource.load.rawbuffer(249 target("dx.Rawbuffer", <4 x i64>, 0, 0) %buffer, i32 %index, i32 0)250 251 ; CHECK63: extractvalue { <4 x i64>, i1 } [[L0]], 0252 ; CHECK63: extractvalue { <4 x i64>, i1 } [[L0]], 1253 254 ; CHECK62-NOT: extractvalue {<4 x i64>, i1 }255 %data0 = extractvalue {<4 x i64>, i1} %load0, 0256 ; check we extract checkbit from both loads and and them together257 ; CHECK62: [[B1:%.*]] = extractvalue { <4 x i32>, i1 } [[L0]], 1258 ; CHECK62: [[B2:%.*]] = extractvalue { <4 x i32>, i1 } [[L2]], 1259 ; CHECK62: and i1 [[B1]], [[B2]]260 %cb = extractvalue {<4 x i64>, i1} %load0, 1261 ret void262}263