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1; RUN: opt -mtriple=dxil-pc-shadermodel6.2-compute -S -dxil-intrinsic-expansion %s | FileCheck %s --check-prefixes=CHECK,CHECK622; RUN: opt -mtriple=dxil-pc-shadermodel6.3-compute -S -dxil-intrinsic-expansion %s | FileCheck %s --check-prefixes=CHECK,CHECK633 4define void @storei64(i64 %0, i32 %index) {5 ; CHECK: [[Buf:%.*]] = tail call target("dx.RawBuffer", i64, 1, 0)6 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i64_1_0t(7 ; CHECK-SAME: i32 0, i32 0, i32 1, i32 0, ptr null)8 %buffer = tail call target("dx.RawBuffer", i64, 1, 0)9 @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_i64_1_0t(10 i32 0, i32 0, i32 1, i32 0, ptr null)11 12 ; check we don't modify the code in sm6.3 or later13 ; CHECK63: call void @llvm.dx.resource.store.rawbuffer14 ; CHECK63-SAME: target("dx.RawBuffer", i64, 1, 0) [[Buf]], i32 %index, i32 0, i64 %0) 15 16 ; check we split the i64 and store the lo and hi bits17 ; CHECK62: [[A:%.*]] = trunc i64 %0 to i3218 ; CHECK62: [[B:%.*]] = lshr i64 %0, 3219 ; CHECK62: [[C:%.*]] = trunc i64 [[B]] to i3220 ; CHECK62: [[Vec1:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i32 021 ; CHECK62: [[Vec2:%.*]] = insertelement <2 x i32> [[Vec1]], i32 [[C]], i32 122 ; CHECK62: call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_i64_1_0t.v2i32(23 ; CHECK62-SAME: target("dx.RawBuffer", i64, 1, 0) [[Buf]], i32 %index, i32 0, <2 x i32> [[Vec2]])24 call void @llvm.dx.resource.store.rawbuffer(25 target("dx.RawBuffer", i64, 1, 0) %buffer, i32 %index, i32 0,26 i64 %0)27 ret void28}29 30define void @storev2i64(<2 x i64> %0, i32 %index) {31 ; CHECK: [[Buf:%.*]] = tail call target("dx.RawBuffer", <2 x i64>, 1, 0)32 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v2i64_1_0t(33 ; CHECK-SAME: i32 0, i32 0, i32 1, i32 0, ptr null)34 %buffer = tail call target("dx.RawBuffer", <2 x i64>, 1, 0)35 @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v2i64_1_0t(36 i32 0, i32 0, i32 1, i32 0, ptr null)37 38 ; check we don't modify the code in sm6.3 or later39 ; CHECK63: call void @llvm.dx.resource.store.rawbuffer40 ; CHECK63-SAME: target("dx.RawBuffer", <2 x i64>, 1, 0) [[Buf]], i32 %index, i32 0, <2 x i64> %0)41 42 ; CHECK62: [[A:%.*]] = trunc <2 x i64> %0 to <2 x i32>43 ; CHECK62: [[B:%.*]] = lshr <2 x i64> %0, splat (i64 32)44 ; CHECK62: [[C:%.*]] = trunc <2 x i64> [[B]] to <2 x i32>45 ; CHECK62: [[Vec:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> [[C]], <4 x i32> <i32 0, i32 2, i32 1, i32 3>46 ; CHECK62: call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v2i64_1_0t.v4i32(47 ; CHECK62-SAME: target("dx.RawBuffer", <2 x i64>, 1, 0) [[Buf]], i32 %index, i32 0, <4 x i32> [[Vec]])48 call void @llvm.dx.resource.store.rawbuffer(49 target("dx.RawBuffer", <2 x i64>, 1, 0) %buffer, i32 %index, i32 0,50 <2 x i64> %0)51 ret void52}53 54define void @storev3i64(<3 x i64> %0, i32 %index) {55 ; CHECK: [[Buf:%.*]] = tail call target("dx.RawBuffer", <3 x i64>, 1, 0)56 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v3i64_1_0t(57 ; CHECK-SAME: i32 0, i32 0, i32 1, i32 0, ptr null)58 %buffer = tail call target("dx.RawBuffer", <3 x i64>, 1, 0)59 @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v3i64_1_0t(60 i32 0, i32 0, i32 1, i32 0, ptr null)61 62 ; check we don't modify the code in sm6.3 or later63 ; CHECK63: call void @llvm.dx.resource.store.rawbuffer64 ; CHECK63-SAME: target("dx.RawBuffer", <3 x i64>, 1, 0) [[Buf]], i32 %index, i32 0, <3 x i64> %0)65 66 ; CHECK62: [[A:%.*]] = trunc <3 x i64> %0 to <3 x i32>67 ; CHECK62: [[B:%.*]] = lshr <3 x i64> %0, splat (i64 32)68 ; CHECK62: [[C:%.*]] = trunc <3 x i64> [[B]] to <3 x i32>69 ; CHECK62: [[D:%.*]] = shufflevector <3 x i32> [[A]], <3 x i32> [[C]], <6 x i32> <i32 0, i32 3, i32 1, i32 4, i32 2, i32 5>70 ; CHECK62: [[E:%.*]] = shufflevector <6 x i32> [[D]], <6 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>71 ; CHECK62: call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v3i64_1_0t.v4i32(target("dx.RawBuffer", <3 x i64>, 1, 0) [[Buf]], i32 %index, i32 0, <4 x i32> [[E]])72 ; CHECK62: [[F:%.*]] = shufflevector <6 x i32> [[D]], <6 x i32> poison, <2 x i32> <i32 4, i32 5>73 ; CHECK62: call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v3i64_1_0t.v2i32(target("dx.RawBuffer", <3 x i64>, 1, 0) [[Buf]], i32 %index, i32 16, <2 x i32> [[F]])74 call void @llvm.dx.resource.store.rawbuffer(75 target("dx.RawBuffer", <3 x i64>, 1, 0) %buffer, i32 %index, i32 0,76 <3 x i64> %0)77 ret void78}79 80define void @storev4i64(<4 x i64> %0, i32 %index) {81 ; CHECK: [[Buf:%.*]] = tail call target("dx.RawBuffer", <4 x i64>, 1, 0)82 ; CHECK-SAME: @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4i64_1_0t(83 ; CHECK-SAME: i32 0, i32 0, i32 1, i32 0, ptr null)84 %buffer = tail call target("dx.RawBuffer", <4 x i64>, 1, 0)85 @llvm.dx.resource.handlefrombinding.tdx.RawBuffer_v4i64_1_0t(86 i32 0, i32 0, i32 1, i32 0, ptr null)87 ; check we don't modify the code in sm6.3 or later88 ; CHECK63: call void @llvm.dx.resource.store.rawbuffer89 ; CHECK63-SAME: target("dx.RawBuffer", <4 x i64>, 1, 0) [[Buf]], i32 %index, i32 0, <4 x i64> %0)90 91 ; CHECK62: [[A:%.*]] = trunc <4 x i64> %0 to <4 x i32>92 ; CHECK62: [[B:%.*]] = lshr <4 x i64> %0, splat (i64 32)93 ; CHECK62: [[C:%.*]] = trunc <4 x i64> [[B]] to <4 x i32>94 ; CHECK62: [[D:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[C]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>95 ; CHECK62: [[E:%.*]] = shufflevector <8 x i32> [[D]], <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>96 ; CHECK62: call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v4i64_1_0t.v4i32(target("dx.RawBuffer", <4 x i64>, 1, 0) [[Buf]], i32 %index, i32 0, <4 x i32> [[E]])97 ; CHECK62: [[F:%.*]] = shufflevector <8 x i32> [[D]], <8 x i32> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>98 ; CHECK62: call void @llvm.dx.resource.store.rawbuffer.tdx.RawBuffer_v4i64_1_0t.v4i32(target("dx.RawBuffer", <4 x i64>, 1, 0) [[Buf]], i32 %index, i32 16, <4 x i32> [[F]])99 call void @llvm.dx.resource.store.rawbuffer(100 target("dx.RawBuffer", <4 x i64>, 1, 0) %buffer, i32 %index, i32 0,101 <4 x i64> %0)102 ret void103}104