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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -passes='dxil-legalize' -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s3 4define void @const_i8_store() {5; CHECK-LABEL: define void @const_i8_store() {6; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 47; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 48; CHECK-NEXT: store i32 1, ptr [[TMP1]], align 49; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 410; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 011; CHECK-NEXT: store i32 [[TMP2]], ptr [[GEP]], align 412; CHECK-NEXT: ret void13;14 %accum.i.flat = alloca [1 x i32], align 415 %i = alloca i8, align 416 store i8 1, ptr %i17 %i8.load = load i8, ptr %i18 %z = zext i8 %i8.load to i3219 %gep = getelementptr i32, ptr %accum.i.flat, i32 020 store i32 %z, ptr %gep, align 421 ret void22}23 24define void @const_add_i8_store() {25; CHECK-LABEL: define void @const_add_i8_store() {26; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 427; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 428; CHECK-NEXT: store i32 4, ptr [[TMP1]], align 429; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 430; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 031; CHECK-NEXT: store i32 [[TMP2]], ptr [[GEP]], align 432; CHECK-NEXT: ret void33;34 %accum.i.flat = alloca [1 x i32], align 435 %i = alloca i8, align 436 %add_i8 = add nsw i8 3, 137 store i8 %add_i8, ptr %i38 %i8.load = load i8, ptr %i39 %z = zext i8 %i8.load to i3240 %gep = getelementptr i32, ptr %accum.i.flat, i32 041 store i32 %z, ptr %gep, align 442 ret void43}44 45define void @var_i8_store(i1 %cmp.i8) {46; CHECK-LABEL: define void @var_i8_store(47; CHECK-SAME: i1 [[CMP_I8:%.*]]) {48; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 449; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 450; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[CMP_I8]], i32 1, i32 251; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 452; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 453; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 054; CHECK-NEXT: store i32 [[TMP3]], ptr [[GEP]], align 455; CHECK-NEXT: ret void56;57 %accum.i.flat = alloca [1 x i32], align 458 %i = alloca i8, align 459 %select.i8 = select i1 %cmp.i8, i8 1, i8 260 store i8 %select.i8, ptr %i61 %i8.load = load i8, ptr %i62 %z = zext i8 %i8.load to i3263 %gep = getelementptr i32, ptr %accum.i.flat, i32 064 store i32 %z, ptr %gep, align 465 ret void66}67 68define void @conflicting_cast(i1 %cmp.i8) {69; CHECK-LABEL: define void @conflicting_cast(70; CHECK-SAME: i1 [[CMP_I8:%.*]]) {71; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [2 x i32], align 472; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 273; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[CMP_I8]], i32 1, i32 274; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 475; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP1]], align 276; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i16, ptr [[ACCUM_I_FLAT]], i32 077; CHECK-NEXT: store i16 [[TMP3]], ptr [[GEP1]], align 278; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i16, ptr [[ACCUM_I_FLAT]], i32 179; CHECK-NEXT: store i16 [[TMP3]], ptr [[GEP2]], align 280; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i3281; CHECK-NEXT: [[GEP3:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 182; CHECK-NEXT: store i32 [[TMP4]], ptr [[GEP3]], align 483; CHECK-NEXT: ret void84;85 %accum.i.flat = alloca [2 x i32], align 486 %i = alloca i8, align 487 %select.i8 = select i1 %cmp.i8, i8 1, i8 288 store i8 %select.i8, ptr %i89 %i8.load = load i8, ptr %i90 %z = zext i8 %i8.load to i1691 %gep1 = getelementptr i16, ptr %accum.i.flat, i32 092 store i16 %z, ptr %gep1, align 293 %gep2 = getelementptr i16, ptr %accum.i.flat, i32 194 store i16 %z, ptr %gep2, align 295 %z2 = zext i8 %i8.load to i3296 %gep3 = getelementptr i32, ptr %accum.i.flat, i32 197 store i32 %z2, ptr %gep3, align 498 ret void99}100