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1; RUN: llc < %s -pre-RA-sched=default2; RUN: llc < %s -pre-RA-sched=list-burr3; RUN: llc < %s -pre-RA-sched=fast4; PR8595 6; The top-down schedulers are excluded here because they don't yet support7; targets that use physreg defs.8 9declare i32 @printf(ptr, i32, float)10 11define i32 @testissue(i32 %i, float %x, float %y) {12 br label %bb113 14bb1: ; preds = %bb1, %015 %x1 = fmul float %x, %y ; <float> [#uses=1]16 %y1 = fmul float %y, 7.500000e-01 ; <float> [#uses=1]17 %z1 = fadd float %x1, %y1 ; <float> [#uses=1]18 %x2 = fmul float %x, 5.000000e-01 ; <float> [#uses=1]19 %y2 = fmul float %y, 0x3FECCCCCC0000000 ; <float> [#uses=1]20 %z2 = fadd float %x2, %y2 ; <float> [#uses=1]21 %z3 = fadd float %z1, %z2 ; <float> [#uses=1]22 %i1 = shl i32 %i, 3 ; <i32> [#uses=1]23 %j1 = add i32 %i, 7 ; <i32> [#uses=1]24 %m1 = add i32 %i1, %j1 ; <i32> [#uses=2]25 %b = icmp sle i32 %m1, 6 ; <i1> [#uses=1]26 br i1 %b, label %bb1, label %bb227 28bb2: ; preds = %bb129 %Msg = inttoptr i64 0 to ptr ; <ptr> [#uses=1]30 call i32 @printf( ptr %Msg, i32 %m1, float %z3 ) ; <i32>:1 [#uses=0]31 ret i32 032}33