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1; RUN: llc -mtriple=hexagon -O2 -mcpu=hexagonv60 -hexagon-initial-cfg-cleanup=0 --stats -o - 2>&1 < %s | FileCheck %s2; This was aborting while processing SUnits.3; REQUIRES: asserts4 5; CHECK: vmem6 7; CHECK-NOT: Number of node order issues found8; CHECK: Number of loops software pipelined9; CHECK-NOT: Number of node order issues found10 11target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"12target triple = "hexagon-unknown--elf"13 14declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #015declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #016declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #017declare <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32>, <16 x i32>, i32) #018declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #019declare <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32>, <16 x i32>) #020declare <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32>, <16 x i32>) #021declare <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32>, <16 x i32>) #022declare <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32>, <16 x i32>, i32) #023 24define void @f0() #1 {25b0:26 %v0 = load ptr, ptr undef, align 427 %v1 = load ptr, ptr undef, align 428 br label %b129 30b1: ; preds = %b3, %b031 %v2 = phi i32 [ 0, %b0 ], [ %v129, %b3 ]32 %v3 = mul nuw nsw i32 %v2, 76833 %v4 = add nuw nsw i32 %v3, 3234 %v5 = add nuw nsw i32 %v3, 6435 %v6 = add nuw nsw i32 %v3, 9636 br label %b237 38b2: ; preds = %b2, %b139 %v7 = phi ptr [ %v1, %b1 ], [ %v127, %b2 ]40 %v8 = phi ptr [ %v0, %b1 ], [ %v128, %b2 ]41 %v9 = phi i32 [ 0, %b1 ], [ %v125, %b2 ]42 %v10 = mul nuw nsw i32 %v9, 3243 %v12 = load <16 x i32>, ptr %v7, align 64, !tbaa !144 %v13 = add nuw nsw i32 %v10, 1645 %v14 = getelementptr inbounds i32, ptr %v1, i32 %v1346 %v16 = load <16 x i32>, ptr %v14, align 64, !tbaa !147 %v17 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v16, <16 x i32> %v12)48 %v18 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v17) #249 %v19 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v17) #250 %v20 = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %v19, <16 x i32> %v18, i32 -4) #251 %v22 = load <16 x i32>, ptr %v8, align 64, !tbaa !452 %v23 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v20) #253 %v24 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v20) #254 %v25 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %v24, <16 x i32> %v23) #255 %v26 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %v24, <16 x i32> %v23) #256 %v27 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %v25, <16 x i32> %v22) #257 %v28 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %v26, <16 x i32> %v22) #258 %v29 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v27) #259 %v30 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v28) #260 %v31 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %v29, <16 x i32> %v30, i32 16) #261 %v32 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v28) #262 %v33 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> undef, <16 x i32> %v32, i32 16) #263 %v34 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v33, <16 x i32> %v31) #264 %v35 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v34) #265 %v36 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v34) #266 %v37 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v36, <16 x i32> %v35, i32 -4) #267 %v38 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v37)68 %v39 = add nuw nsw i32 %v10, %v369 %v40 = getelementptr inbounds i32, ptr undef, i32 %v3970 store <16 x i32> %v38, ptr %v40, align 64, !tbaa !671 %v42 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v37)72 store <16 x i32> %v42, ptr undef, align 64, !tbaa !673 %v43 = getelementptr i32, ptr %v7, i32 3274 %v44 = getelementptr i16, ptr %v8, i32 3275 %v46 = load <16 x i32>, ptr %v43, align 64, !tbaa !176 %v47 = add nuw nsw i32 %v10, 4877 %v48 = getelementptr inbounds i32, ptr %v1, i32 %v4778 %v50 = load <16 x i32>, ptr %v48, align 64, !tbaa !179 %v51 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v50, <16 x i32> %v46)80 %v52 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v51) #281 %v53 = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> undef, <16 x i32> %v52, i32 -4) #282 %v55 = load <16 x i32>, ptr %v44, align 64, !tbaa !483 %v56 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v53) #284 %v57 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> undef, <16 x i32> %v56) #285 %v58 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> undef, <16 x i32> %v56) #286 %v59 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %v57, <16 x i32> %v55) #287 %v60 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %v58, <16 x i32> %v55) #288 %v61 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v59) #289 %v62 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %v61, <16 x i32> undef, i32 16) #290 %v63 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v59) #291 %v64 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v60) #292 %v65 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %v63, <16 x i32> %v64, i32 16) #293 %v66 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v65, <16 x i32> %v62) #294 %v67 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v66) #295 %v68 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v66) #296 %v69 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v68, <16 x i32> %v67, i32 -4) #297 %v70 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v69)98 %v71 = add nuw nsw i32 %v4, %v1099 %v72 = getelementptr inbounds i32, ptr undef, i32 %v71100 store <16 x i32> %v70, ptr %v72, align 64, !tbaa !6101 %v74 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v69)102 %v75 = add nuw nsw i32 %v71, 16103 %v76 = getelementptr inbounds i32, ptr undef, i32 %v75104 store <16 x i32> %v74, ptr %v76, align 64, !tbaa !6105 %v78 = getelementptr i32, ptr %v7, i32 64106 %v79 = getelementptr i16, ptr %v8, i32 64107 %v81 = load <16 x i32>, ptr %v78, align 64, !tbaa !1108 %v82 = add nuw nsw i32 %v10, 80109 %v83 = getelementptr inbounds i32, ptr %v1, i32 %v82110 %v85 = load <16 x i32>, ptr %v83, align 64, !tbaa !1111 %v86 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v85, <16 x i32> %v81)112 %v87 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v86) #2113 %v88 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v86) #2114 %v89 = tail call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %v88, <16 x i32> %v87, i32 -4) #2115 %v91 = load <16 x i32>, ptr %v79, align 64, !tbaa !4116 %v92 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v89) #2117 %v93 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v89) #2118 %v94 = tail call <16 x i32> @llvm.hexagon.V6.vshufeh(<16 x i32> %v93, <16 x i32> %v92) #2119 %v95 = tail call <16 x i32> @llvm.hexagon.V6.vshufoh(<16 x i32> %v93, <16 x i32> %v92) #2120 %v96 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %v94, <16 x i32> %v91) #2121 %v97 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv(<16 x i32> %v95, <16 x i32> %v91) #2122 %v98 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v97) #2123 %v99 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> undef, <16 x i32> %v98, i32 16) #2124 %v100 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v96) #2125 %v101 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v97) #2126 %v102 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %v100, <16 x i32> %v101, i32 16) #2127 %v103 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v102, <16 x i32> %v99) #2128 %v104 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v103) #2129 %v105 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v103) #2130 %v106 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> %v105, <16 x i32> %v104, i32 -4) #2131 %v107 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v106)132 %v108 = add nuw nsw i32 %v5, %v10133 %v109 = getelementptr inbounds i32, ptr undef, i32 %v108134 store <16 x i32> %v107, ptr %v109, align 64, !tbaa !6135 %v111 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v106)136 %v112 = add nuw nsw i32 %v108, 16137 %v113 = getelementptr inbounds i32, ptr undef, i32 %v112138 store <16 x i32> %v111, ptr %v113, align 64, !tbaa !6139 %v115 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> undef) #2140 %v116 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %v115, i32 -4) #2141 %v117 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v116)142 %v118 = add nuw nsw i32 %v6, %v10143 %v119 = getelementptr inbounds i32, ptr undef, i32 %v118144 store <16 x i32> %v117, ptr %v119, align 64, !tbaa !6145 %v121 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v116)146 %v122 = add nuw nsw i32 %v118, 16147 %v123 = getelementptr inbounds i32, ptr undef, i32 %v122148 store <16 x i32> %v121, ptr %v123, align 64, !tbaa !6149 %v125 = add nuw nsw i32 %v9, 4150 %v126 = icmp eq i32 %v125, 24151 %v127 = getelementptr i32, ptr %v7, i32 128152 %v128 = getelementptr i16, ptr %v8, i32 128153 br i1 %v126, label %b3, label %b2154 155b3: ; preds = %b2156 %v129 = add nuw nsw i32 %v2, 1157 br label %b1158}159 160attributes #0 = { nounwind readnone }161attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }162attributes #2 = { nounwind }163 164!llvm.module.flags = !{!0}165 166!0 = !{i32 2, !"halide_mattrs", !"+hvx"}167!1 = !{!2, !2, i64 0}168!2 = !{!"in_u32", !3}169!3 = !{!"Halide buffer"}170!4 = !{!5, !5, i64 0}171!5 = !{!"in_u16", !3}172!6 = !{!7, !7, i64 0}173!7 = !{!"op_vmpy_v__uh_v__uh__1", !3}174