51 lines · plain
1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Make sure that the addressing mode optimization does not propagate4; an add instruction where the base register would have a different5; reaching def.6 7; CHECK-LABEL: f0.1:8; CHECK-LABEL: %b09; CHECK: r17 = add(r{{[0-9]+}},#8)10; CHECK-LABEL: %b111; CHECK: r16 = r012; CHECK-LABEL: %b213; CHECK: memd(r17+#0)14 15target triple = "hexagon"16 17%s.0 = type { i8, i8, %s.1, i32 }18%s.1 = type { %s.2, [128 x i8] }19%s.2 = type { i8, i8, i64, %s.3 }20%s.3 = type { i8 }21 22define void @f0.1() local_unnamed_addr #0 align 2 {23b0:24 %v0 = alloca %s.0, align 825 %v1 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 126 store i8 4, ptr %v1, align 127 %v2 = call signext i8 @f1.2(ptr undef) #028 %v3 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 2, i32 0, i32 029 %v4 = getelementptr inbounds %s.0, ptr %v0, i32 0, i32 2, i32 0, i32 3, i32 030 store i8 -1, ptr %v4, align 831 br i1 undef, label %b1, label %b232 33b1: ; preds = %b034 %v5 = call dereferenceable(12) ptr @f2.3(ptr nonnull undef, ptr nonnull dereferenceable(80) undef) #035 %v6 = call signext i8 @f1.2(ptr undef) #036 %v7 = call dereferenceable(12) ptr @f3(ptr nonnull %v5, i16 signext undef) #037 br label %b238 39b2: ; preds = %b1, %b040 call void @llvm.memcpy.p0.p0.i32(ptr align 8 undef, ptr align 8 %v3, i32 48, i1 false)41 ret void42}43 44declare signext i8 @f1.2(ptr) #045declare dereferenceable(12) ptr @f2.3(ptr, ptr dereferenceable(80)) #046declare dereferenceable(12) ptr @f3(ptr, i16 signext) #047declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) #148 49attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-long-calls" }50attributes #1 = { argmemonly nounwind }51