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1; RUN: llc -mtriple=hexagon -O3 < %s | FileCheck %s2 3; CHECK-NOT: [[REG0:(r[0-9]+)]] = memw([[REG0:(r[0-9]+)]]<<#2+##state-4)4 5%s.0 = type { i16, [10 x ptr] }6%s.1 = type { %s.2, i16, i16 }7%s.2 = type { i8, [15 x %s.3], [18 x %s.4], %s.5, i16 }8%s.3 = type { %s.5, ptr, ptr, i16, i8, i8, [3 x ptr], [3 x ptr], [3 x ptr] }9%s.4 = type { %s.5, ptr, i8, i16, i8 }10%s.5 = type { ptr, ptr }11%s.6 = type { i8, i8 }12 13@g0 = common global %s.0 zeroinitializer, align 414 15; Function Attrs: nounwind optsize16define void @f0(ptr nocapture readonly %a0) local_unnamed_addr #0 {17b0:18 %v1 = getelementptr %s.6, ptr %a0, i32 0, i32 119 %v2 = load i8, ptr %v1, align 120 %v3 = zext i8 %v2 to i3221 %v4 = add nsw i32 %v3, -122 %v5 = getelementptr %s.0, ptr @g0, i32 0, i32 123 %v6 = getelementptr [10 x ptr], ptr %v5, i32 0, i32 %v424 %v7 = load ptr, ptr %v6, align 425 %v8 = icmp eq ptr %v7, null26 br i1 %v8, label %b4, label %b127 28b1: ; preds = %b029 %v11 = load i8, ptr %v7, align 430 %v12 = icmp eq i8 %v11, %v231 br i1 %v12, label %b2, label %b432 33b2: ; preds = %b134 tail call void @f1(ptr nonnull %v7) #235 %v14 = getelementptr %s.6, ptr %a0, i32 0, i32 136 %v15 = load i8, ptr %v14, align 137 %v16 = zext i8 %v15 to i3238 %v17 = add nsw i32 %v16, -139 %v18 = getelementptr [10 x ptr], ptr %v5, i32 0, i32 %v1740 %v19 = load ptr, ptr %v18, align 441 %v20 = icmp eq ptr %v19, null42 br i1 %v20, label %b4, label %b343 44b3: ; preds = %b245 %v21 = getelementptr %s.1, ptr %v19, i32 0, i32 0, i32 346 tail call void @f2(ptr %v21) #247 store ptr null, ptr %v18, align 448 br label %b449 50b4: ; preds = %b3, %b2, %b1, %b051 ret void52}53 54; Function Attrs: optsize55declare void @f1(ptr) #156 57; Function Attrs: optsize58declare void @f2(ptr) #159 60attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }61attributes #1 = { optsize "target-cpu"="hexagonv60" "target-features"="+hvx" }62attributes #2 = { nounwind }63