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1; RUN: llc -march=hexagon < %s | FileCheck %s2 3; Test for saturating add instructions.4 5; CHECK-LABEL: test16; CHECK: v{{.*}}.ub = vadd(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub):sat7define <128 x i8> @test1(<128 x i8>* %a0, <128 x i8>* %a1) #0 {8entry:9 %wide.load = load <128 x i8>, <128 x i8>* %a0, align 110 %wide.load62 = load <128 x i8>, <128 x i8>* %a1, align 111 %add = call <128 x i8> @llvm.uadd.sat.v128i8(<128 x i8> %wide.load, <128 x i8> %wide.load62)12 ret <128 x i8> %add13}14 15; CHECK-LABEL: test216; CHECK: v{{.*}}.b = vadd(v{{[0-9]+}}.b,v{{[0-9]+}}.b):sat17define <128 x i8> @test2(<128 x i8>* %a0, <128 x i8>* %a1) #0 {18entry:19 %wide.load = load <128 x i8>, <128 x i8>* %a0, align 120 %wide.load62 = load <128 x i8>, <128 x i8>* %a1, align 121 %add = call <128 x i8> @llvm.sadd.sat.v128i8(<128 x i8> %wide.load, <128 x i8> %wide.load62)22 ret <128 x i8> %add23}24 25; CHECK-LABEL: test326; CHECK: v{{.*}}.uh = vadd(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh):sat27define <64 x i16> @test3(<64 x i16>* %a0, <64 x i16>* %a1) #0 {28entry:29 %wide.load = load <64 x i16>, <64 x i16>* %a0, align 130 %wide.load62 = load <64 x i16>, <64 x i16>* %a1, align 131 %add = call <64 x i16> @llvm.uadd.sat.v64i16(<64 x i16> %wide.load, <64 x i16> %wide.load62)32 ret <64 x i16> %add33}34 35; CHECK-LABEL: test436; CHECK: v{{.*}}.h = vadd(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat37define <64 x i16> @test4(<64 x i16>* %a0, <64 x i16>* %a1) #0 {38entry:39 %wide.load = load <64 x i16>, <64 x i16>* %a0, align 140 %wide.load62 = load <64 x i16>, <64 x i16>* %a1, align 141 %add = call <64 x i16> @llvm.sadd.sat.v64i16(<64 x i16> %wide.load, <64 x i16> %wide.load62)42 ret <64 x i16> %add43}44 45; CHECK-LABEL: test546; CHECK: v{{.*}}.uw = vadd(v{{[0-9]+}}.uw,v{{[0-9]+}}.uw):sat47define <32 x i32> @test5(<32 x i32>* %a0, <32 x i32>* %a1) #0 {48entry:49 %wide.load = load <32 x i32>, <32 x i32>* %a0, align 150 %wide.load62 = load <32 x i32>, <32 x i32>* %a1, align 151 %add = call <32 x i32> @llvm.uadd.sat.v32i32(<32 x i32> %wide.load, <32 x i32> %wide.load62)52 ret <32 x i32> %add53}54 55; CHECK-LABEL: test656; CHECK: v{{.*}}.w = vadd(v{{[0-9]+}}.w,v{{[0-9]+}}.w):sat57define <32 x i32> @test6(<32 x i32>* %a0, <32 x i32>* %a1) #0 {58entry:59 %wide.load = load <32 x i32>, <32 x i32>* %a0, align 160 %wide.load62 = load <32 x i32>, <32 x i32>* %a1, align 161 %add = call <32 x i32> @llvm.sadd.sat.v32i32(<32 x i32> %wide.load, <32 x i32> %wide.load62)62 ret <32 x i32> %add63}64 65; CHECK-LABEL: test766; CHECK: v{{[0-9]+}}:{{[0-9]+}}.ub = vadd(v{{[0-9]+}}:{{[0-9]+}}.ub,v{{[0-9]+}}:{{[0-9]+}}.ub):sat67define <256 x i8> @test7(<256 x i8>* %a0, <256 x i8>* %a1) #0 {68entry:69 %wide.load = load <256 x i8>, <256 x i8>* %a0, align 170 %wide.load62 = load <256 x i8>, <256 x i8>* %a1, align 171 %add = call <256 x i8> @llvm.uadd.sat.v256i8(<256 x i8> %wide.load, <256 x i8> %wide.load62)72 ret <256 x i8> %add73}74 75; CHECK-LABEL: test876; CHECK: v{{[0-9]+}}:{{[0-9]+}}.b = vadd(v{{[0-9]+}}:{{[0-9]+}}.b,v{{[0-9]+}}:{{[0-9]+}}.b):sat77define <256 x i8> @test8(<256 x i8>* %a0, <256 x i8>* %a1) #0 {78entry:79 %wide.load = load <256 x i8>, <256 x i8>* %a0, align 180 %wide.load62 = load <256 x i8>, <256 x i8>* %a1, align 181 %add = call <256 x i8> @llvm.sadd.sat.v256i8(<256 x i8> %wide.load, <256 x i8> %wide.load62)82 ret <256 x i8> %add83}84 85; CHECK-LABEL: test986; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh = vadd(v{{[0-9]+}}:{{[0-9]+}}.uh,v{{[0-9]+}}:{{[0-9]+}}.uh):sat87define <128 x i16> @test9(<128 x i16>* %a0, <128 x i16>* %a1) #0 {88entry:89 %wide.load = load <128 x i16>, <128 x i16>* %a0, align 190 %wide.load62 = load <128 x i16>, <128 x i16>* %a1, align 191 %add = call <128 x i16> @llvm.uadd.sat.v128i16(<128 x i16> %wide.load, <128 x i16> %wide.load62)92 ret <128 x i16> %add93}94 95; CHECK-LABEL: test1096; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h = vadd(v{{[0-9]+}}:{{[0-9]+}}.h,v{{[0-9]+}}:{{[0-9]+}}.h):sat97define <128 x i16> @test10(<128 x i16>* %a0, <128 x i16>* %a1) #0 {98entry:99 %wide.load = load <128 x i16>, <128 x i16>* %a0, align 1100 %wide.load62 = load <128 x i16>, <128 x i16>* %a1, align 1101 %add = call <128 x i16> @llvm.sadd.sat.v128i16(<128 x i16> %wide.load, <128 x i16> %wide.load62)102 ret <128 x i16> %add103}104 105; CHECK-LABEL: test11106; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw = vadd(v{{[0-9]+}}:{{[0-9]+}}.uw,v{{[0-9]+}}:{{[0-9]+}}.uw):sat107define <64 x i32> @test11(<64 x i32>* %a0, <64 x i32>* %a1) #0 {108entry:109 %wide.load = load <64 x i32>, <64 x i32>* %a0, align 1110 %wide.load62 = load <64 x i32>, <64 x i32>* %a1, align 1111 %add = call <64 x i32> @llvm.uadd.sat.v64i32(<64 x i32> %wide.load, <64 x i32> %wide.load62)112 ret <64 x i32> %add113}114 115; CHECK-LABEL: test12116; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w = vadd(v{{[0-9]+}}:{{[0-9]+}}.w,v{{[0-9]+}}:{{[0-9]+}}.w):sat117define <64 x i32> @test12(<64 x i32>* %a0, <64 x i32>* %a1) #0 {118entry:119 %wide.load = load <64 x i32>, <64 x i32>* %a0, align 1120 %wide.load62 = load <64 x i32>, <64 x i32>* %a1, align 1121 %add = call <64 x i32> @llvm.sadd.sat.v64i32(<64 x i32> %wide.load, <64 x i32> %wide.load62)122 ret <64 x i32> %add123}124 125; CHECK-LABEL: test13126; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},r{{[0-9]+}}):sat127define i32 @test13(i32 %a0, i32 %a1) #0 {128entry:129 %add = call i32 @llvm.sadd.sat.i32(i32 %a0, i32 %a1)130 ret i32 %add131}132 133; CHECK-LABEL: test14134; CHECK: r{{[0-9]+}}:{{[0-9]+}} = add(r{{[0-9]+}}:{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}}):sat135define i64 @test14(i64 %a0, i64 %a1) #0 {136entry:137 %add = call i64 @llvm.sadd.sat.i64(i64 %a0, i64 %a1)138 ret i64 %add139}140 141declare <128 x i8> @llvm.uadd.sat.v128i8(<128 x i8>, <128 x i8>) #1142declare <128 x i8> @llvm.sadd.sat.v128i8(<128 x i8>, <128 x i8>) #1143declare <64 x i16> @llvm.uadd.sat.v64i16(<64 x i16>, <64 x i16>) #1144declare <64 x i16> @llvm.sadd.sat.v64i16(<64 x i16>, <64 x i16>) #1145declare <32 x i32> @llvm.uadd.sat.v32i32(<32 x i32>, <32 x i32>) #1146declare <32 x i32> @llvm.sadd.sat.v32i32(<32 x i32>, <32 x i32>) #1147declare <256 x i8> @llvm.uadd.sat.v256i8(<256 x i8>, <256 x i8>) #1148declare <256 x i8> @llvm.sadd.sat.v256i8(<256 x i8>, <256 x i8>) #1149declare <128 x i16> @llvm.uadd.sat.v128i16(<128 x i16>, <128 x i16>) #1150declare <128 x i16> @llvm.sadd.sat.v128i16(<128 x i16>, <128 x i16>) #1151declare <64 x i32> @llvm.uadd.sat.v64i32(<64 x i32>, <64 x i32>) #1152declare <64 x i32> @llvm.sadd.sat.v64i32(<64 x i32>, <64 x i32>) #1153declare i32 @llvm.sadd.sat.i32(i32, i32)154declare i64 @llvm.sadd.sat.i64(i64, i64)155 156attributes #0 = { nounwind "target-cpu"="hexagonv73" "target-features"="+hvxv73,+hvx-length128b" }157attributes #1 = { nounwind readnone speculatable willreturn }158