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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=hexagon < %s | FileCheck %s3;4; Check if we generate rounding-asr instruction. It is equivalent to5; Rd = ((Rs >> #u) +1) >> 1.6target triple = "hexagon"7 8; Function Attrs: nounwind9define i32 @f0(i32 %a0) #0 {10; CHECK-LABEL: f0:11; CHECK: // %bb.0: // %b012; CHECK-NEXT: {13; CHECK-NEXT: r0 = asr(r0,#10):rnd14; CHECK-NEXT: r1 = r015; CHECK-NEXT: r29 = add(r29,#-8)16; CHECK-NEXT: }17; CHECK-NEXT: {18; CHECK-NEXT: r29 = add(r29,#8)19; CHECK-NEXT: jumpr r3120; CHECK-NEXT: memw(r29+#4) = r121; CHECK-NEXT: }22b0:23 %v0 = alloca i32, align 424 store i32 %a0, ptr %v0, align 425 %v1 = load i32, ptr %v0, align 426 %v2 = ashr i32 %v1, 1027 %v3 = add nsw i32 %v2, 128 %v4 = ashr i32 %v3, 129 ret i32 %v430}31 32; Function Attrs: nounwind33define i64 @f1(i64 %a0) #0 {34; CHECK-LABEL: f1:35; CHECK: // %bb.0: // %b036; CHECK-NEXT: {37; CHECK-NEXT: r1:0 = asr(r1:0,#17):rnd38; CHECK-NEXT: r3:2 = combine(r1,r0)39; CHECK-NEXT: r29 = add(r29,#-8)40; CHECK-NEXT: }41; CHECK-NEXT: {42; CHECK-NEXT: r29 = add(r29,#8)43; CHECK-NEXT: jumpr r3144; CHECK-NEXT: memd(r29+#0) = r3:245; CHECK-NEXT: }46b0:47 %v0 = alloca i64, align 848 store i64 %a0, ptr %v0, align 849 %v1 = load i64, ptr %v0, align 850 %v2 = ashr i64 %v1, 1751 %v3 = add nsw i64 %v2, 152 %v4 = ashr i64 %v3, 153 ret i64 %v454}55 56attributes #0 = { nounwind }57