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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=hexagon < %s | FileCheck %s3;4; Check if we generate rounding-asr instruction. It is equivalent to5; Rd = ((Rs >> #u) +1) >> 1.6 7target triple = "hexagon"8 9define i32 @f0(i32 %a0) {10; CHECK-LABEL: f0:11; CHECK: .cfi_startproc12; CHECK-NEXT: // %bb.0: // %b013; CHECK-NEXT: {14; CHECK-NEXT: r0 = asr(r0,#10):rnd15; CHECK-NEXT: r1 = r016; CHECK-NEXT: r29 = add(r29,#-8)17; CHECK-NEXT: }18; CHECK-NEXT: {19; CHECK-NEXT: r29 = add(r29,#8)20; CHECK-NEXT: jumpr r3121; CHECK-NEXT: memw(r29+#4) = r122; CHECK-NEXT: }23b0:24 %v0 = alloca i32, align 425 store i32 %a0, ptr %v0, align 426 %v1 = load i32, ptr %v0, align 427 %v2 = ashr i32 %v1, 1028 %v3 = add nsw i32 %v2, 129 %v4 = ashr i32 %v3, 130 ret i32 %v431}32 33define i64 @f1(i64 %a0) {34; CHECK-LABEL: f1:35; CHECK: .cfi_startproc36; CHECK-NEXT: // %bb.0: // %b037; CHECK-NEXT: {38; CHECK-NEXT: r1:0 = asr(r1:0,#17):rnd39; CHECK-NEXT: r3:2 = combine(r1,r0)40; CHECK-NEXT: r29 = add(r29,#-8)41; CHECK-NEXT: }42; CHECK-NEXT: {43; CHECK-NEXT: r29 = add(r29,#8)44; CHECK-NEXT: jumpr r3145; CHECK-NEXT: memd(r29+#0) = r3:246; CHECK-NEXT: }47b0:48 %v0 = alloca i64, align 849 store i64 %a0, ptr %v0, align 850 %v1 = load i64, ptr %v0, align 851 %v2 = ashr i64 %v1, 1752 %v3 = add nsw i64 %v2, 153 %v4 = ashr i64 %v3, 154 ret i64 %v455}56