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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define <64 x half> @f0(<64 x half> %a0, <64 x half> %a1) #0 {5; CHECK-LABEL: f0:6; CHECK: // %bb.0: // %b07; CHECK-NEXT: {8; CHECK-NEXT: v0.qf16 = vadd(v0.hf,v1.hf)9; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: v0.hf = v0.qf1612; CHECK-NEXT: jumpr r3113; CHECK-NEXT: }14b0:15 %v0 = fadd <64 x half> %a0, %a116 ret <64 x half> %v017}18 19define <32 x float> @f1(<32 x float> %a0, <32 x float> %a1) #0 {20; CHECK-LABEL: f1:21; CHECK: // %bb.0: // %b022; CHECK-NEXT: {23; CHECK-NEXT: v0.qf32 = vadd(v0.sf,v1.sf)24; CHECK-NEXT: }25; CHECK-NEXT: {26; CHECK-NEXT: v0.sf = v0.qf3227; CHECK-NEXT: jumpr r3128; CHECK-NEXT: }29b0:30 %v0 = fadd <32 x float> %a0, %a131 ret <32 x float> %v032}33 34define <64 x half> @f2(<64 x half> %a0, <64 x half> %a1) #0 {35; CHECK-LABEL: f2:36; CHECK: // %bb.0: // %b037; CHECK-NEXT: {38; CHECK-NEXT: v0.qf16 = vsub(v0.hf,v1.hf)39; CHECK-NEXT: }40; CHECK-NEXT: {41; CHECK-NEXT: v0.hf = v0.qf1642; CHECK-NEXT: jumpr r3143; CHECK-NEXT: }44b0:45 %v0 = fsub <64 x half> %a0, %a146 ret <64 x half> %v047}48 49define <32 x float> @f3(<32 x float> %a0, <32 x float> %a1) #0 {50; CHECK-LABEL: f3:51; CHECK: // %bb.0: // %b052; CHECK-NEXT: {53; CHECK-NEXT: v0.qf32 = vsub(v0.sf,v1.sf)54; CHECK-NEXT: }55; CHECK-NEXT: {56; CHECK-NEXT: v0.sf = v0.qf3257; CHECK-NEXT: jumpr r3158; CHECK-NEXT: }59b0:60 %v0 = fsub <32 x float> %a0, %a161 ret <32 x float> %v062}63 64define <64 x half> @f4(<64 x half> %a0, <64 x half> %a1) #0 {65; CHECK-LABEL: f4:66; CHECK: // %bb.0: // %b067; CHECK-NEXT: {68; CHECK-NEXT: v0.qf16 = vmpy(v0.hf,v1.hf)69; CHECK-NEXT: }70; CHECK-NEXT: {71; CHECK-NEXT: v0.hf = v0.qf1672; CHECK-NEXT: jumpr r3173; CHECK-NEXT: }74b0:75 %v0 = fmul <64 x half> %a0, %a176 ret <64 x half> %v077}78 79define <32 x float> @f5(<32 x float> %a0, <32 x float> %a1) #0 {80; CHECK-LABEL: f5:81; CHECK: // %bb.0: // %b082; CHECK-NEXT: {83; CHECK-NEXT: v0.qf32 = vmpy(v0.sf,v1.sf)84; CHECK-NEXT: }85; CHECK-NEXT: {86; CHECK-NEXT: v0.sf = v0.qf3287; CHECK-NEXT: jumpr r3188; CHECK-NEXT: }89b0:90 %v0 = fmul <32 x float> %a0, %a191 ret <32 x float> %v092}93 94define <64 x half> @f6(<64 x half> %a0, <64 x half> %a1) #1 {95; CHECK-LABEL: f6:96; CHECK: // %bb.0: // %b097; CHECK-NEXT: {98; CHECK-NEXT: v0.hf = vadd(v0.hf,v1.hf)99; CHECK-NEXT: jumpr r31100; CHECK-NEXT: }101b0:102 %v0 = fadd <64 x half> %a0, %a1103 ret <64 x half> %v0104}105 106define <32 x float> @f7(<32 x float> %a0, <32 x float> %a1) #1 {107; CHECK-LABEL: f7:108; CHECK: // %bb.0: // %b0109; CHECK-NEXT: {110; CHECK-NEXT: v0.sf = vadd(v0.sf,v1.sf)111; CHECK-NEXT: jumpr r31112; CHECK-NEXT: }113b0:114 %v0 = fadd <32 x float> %a0, %a1115 ret <32 x float> %v0116}117 118define <64 x half> @f8(<64 x half> %a0, <64 x half> %a1) #1 {119; CHECK-LABEL: f8:120; CHECK: // %bb.0: // %b0121; CHECK-NEXT: {122; CHECK-NEXT: v0.hf = vsub(v0.hf,v1.hf)123; CHECK-NEXT: jumpr r31124; CHECK-NEXT: }125b0:126 %v0 = fsub <64 x half> %a0, %a1127 ret <64 x half> %v0128}129 130define <32 x float> @f9(<32 x float> %a0, <32 x float> %a1) #1 {131; CHECK-LABEL: f9:132; CHECK: // %bb.0: // %b0133; CHECK-NEXT: {134; CHECK-NEXT: v0.sf = vsub(v0.sf,v1.sf)135; CHECK-NEXT: jumpr r31136; CHECK-NEXT: }137b0:138 %v0 = fsub <32 x float> %a0, %a1139 ret <32 x float> %v0140}141 142define <64 x half> @f10(<64 x half> %a0, <64 x half> %a1) #1 {143; CHECK-LABEL: f10:144; CHECK: // %bb.0: // %b0145; CHECK-NEXT: {146; CHECK-NEXT: v0.hf = vmpy(v0.hf,v1.hf)147; CHECK-NEXT: jumpr r31148; CHECK-NEXT: }149b0:150 %v0 = fmul <64 x half> %a0, %a1151 ret <64 x half> %v0152}153 154define <32 x float> @f11(<32 x float> %a0, <32 x float> %a1) #1 {155; CHECK-LABEL: f11:156; CHECK: // %bb.0: // %b0157; CHECK-NEXT: {158; CHECK-NEXT: v0.sf = vmpy(v0.sf,v1.sf)159; CHECK-NEXT: jumpr r31160; CHECK-NEXT: }161b0:162 %v0 = fmul <32 x float> %a0, %a1163 ret <32 x float> %v0164}165 166attributes #0 = { nounwind "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" }167attributes #1 = { nounwind "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-ieee-fp" }168