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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; CHECK-LABEL: f04; CHECK: v[[V00:[0-9]+]]:[[V01:[0-9]+]].uh = vzxt(v0.ub)5; CHECK-DAG: v[[V02:[0-9]+]].h = vpopcount(v[[V00]].h)6; CHECK-DAG: v[[V03:[0-9]+]].h = vpopcount(v[[V01]].h)7; CHECK: v0.b = vshuffe(v[[V02]].b,v[[V03]].b)8define <128 x i8> @f0(<128 x i8> %a0) #0 {9 %t0 = call <128 x i8> @llvm.ctpop.v128i8(<128 x i8> %a0)10 ret <128 x i8> %t011}12 13; CHECK-LABEL: f114; CHECK: v0.h = vpopcount(v0.h)15define <64 x i16> @f1(<64 x i16> %a0) #0 {16 %t0 = call <64 x i16> @llvm.ctpop.v64i16(<64 x i16> %a0)17 ret <64 x i16> %t018}19 20; CHECK-LABEL: f221; CHECK: v[[V20:[0-9]+]].h = vpopcount(v0.h)22; CHECK: v[[V21:[0-9]+]]:[[V22:[0-9]+]].uw = vzxt(v[[V20]].uh)23; CHECK: v0.w = vadd(v[[V22]].w,v[[V21]].w)24define <32 x i32> @f2(<32 x i32> %a0) #0 {25 %t0 = call <32 x i32> @llvm.ctpop.v32i32(<32 x i32> %a0)26 ret <32 x i32> %t027}28 29; CHECK-LABEL: f330; CHECK-DAG: r[[R30:[0-9]+]] = ##13474407231; CHECK-DAG: v[[V31:[0-9]+]]:[[V32:[0-9]+]].uh = vzxt(v0.ub)32; CHECK: v[[V33:[0-9]+]] = vsplat(r[[R30]])33; CHECK-DAG: v[[V34:[0-9]+]].uh = vcl0(v[[V31]].uh)34; CHECK-DAG: v[[V35:[0-9]+]].uh = vcl0(v[[V32]].uh)35; CHECK: v[[V36:[0-9]+]].b = vshuffe(v[[V34]].b,v[[V35]].b)36; CHECK: v0.b = vsub(v[[V36]].b,v[[V33]].b)37define <128 x i8> @f3(<128 x i8> %a0) #0 {38 %t0 = call <128 x i8> @llvm.ctlz.v128i8(<128 x i8> %a0)39 ret <128 x i8> %t040}41 42; CHECK-LABEL: f443; CHECK: v0.uh = vcl0(v0.uh)44define <64 x i16> @f4(<64 x i16> %a0) #0 {45 %t0 = call <64 x i16> @llvm.ctlz.v64i16(<64 x i16> %a0)46 ret <64 x i16> %t047}48 49; CHECK-LABEL: f550; CHECK: v0.uw = vcl0(v0.uw)51define <32 x i32> @f5(<32 x i32> %a0) #0 {52 %t0 = call <32 x i32> @llvm.ctlz.v32i32(<32 x i32> %a0)53 ret <32 x i32> %t054}55 56; CHECK-LABEL: f657; r = 0x0101010158; CHECK-DAG: r[[R60:[0-9]+]] = ##1684300959; CHECK-DAG: v[[V61:[0-9]+]] = vnot(v0)60; r = 0x0808080861; CHECK-DAG: r[[R62:[0-9]+]] = ##13474407262; CHECK: v[[V63:[0-9]+]] = vsplat(r[[R60]])63; CHECK-DAG: v[[V64:[0-9]+]] = vsplat(r[[R62]])64; CHECK: v[[V65:[0-9]+]].b = vsub(v0.b,v[[V63]].b)65; CHECK: v[[V66:[0-9]+]] = vand(v[[V61]],v[[V65]])66; Ctlz:67; CHECK: v[[V67:[0-9]+]]:[[V68:[0-9]+]].uh = vzxt(v[[V66]].ub)68; CHECK: v[[V69:[0-9]+]].uh = vcl0(v[[V68]].uh)69; CHECK: v[[V6A:[0-9]+]].uh = vcl0(v[[V67]].uh)70; CHECK: v[[V6B:[0-9]+]].b = vshuffe(v[[V6A]].b,v[[V69]].b)71; CHECK: v[[V6C:[0-9]+]].b = vsub(v[[V6B]].b,v[[V64]].b)72; CHECK: v0.b = vsub(v[[V64]].b,v[[V6C]].b)73define <128 x i8> @f6(<128 x i8> %a0) #0 {74 %t0 = call <128 x i8> @llvm.cttz.v128i8(<128 x i8> %a0)75 ret <128 x i8> %t076}77 78; CHECK-LABEL: f779; r = 0x0001000180; CHECK-DAG: r[[R70:[0-9]+]] = ##6553781; CHECK-DAG: v[[V71:[0-9]+]] = vnot(v0)82; r = 0x00100010 // halfword bitwidths83; CHECK-DAG: r[[R72:[0-9]+]] = ##104859284; CHECK: v[[V73:[0-9]+]] = vsplat(r[[R70]])85; CHECK: v[[V74:[0-9]+]] = vsplat(r[[R72]])86; CHECK: v[[V75:[0-9]+]].h = vsub(v0.h,v[[V73]].h)87; CHECK: v[[V76:[0-9]+]] = vand(v[[V71]],v[[V75]])88; Ctlz:89; CHECK: v[[V77:[0-9]+]].uh = vcl0(v[[V76]].uh)90; CHECK: v0.h = vsub(v[[V74]].h,v[[V77]].h)91define <64 x i16> @f7(<64 x i16> %a0) #0 {92 %t0 = call <64 x i16> @llvm.cttz.v64i16(<64 x i16> %a0)93 ret <64 x i16> %t094}95 96; CHECK-LABEL: f897; CHECK-DAG: r[[R80:[0-9]+]] = #198; CHECK-DAG: v[[V81:[0-9]+]] = vnot(v0)99; CHECK-DAG: r[[R82:[0-9]+]] = #32100; CHECK: v[[V83:[0-9]+]] = vsplat(r[[R80]])101; CHECK: v[[V84:[0-9]+]] = vsplat(r[[R82]])102; CHECK: v[[V85:[0-9]+]].w = vsub(v0.w,v[[V83]].w)103; CHECK: v[[V86:[0-9]+]] = vand(v[[V81]],v[[V85]])104; Ctlz:105; CHECK: v[[V87:[0-9]+]].uw = vcl0(v[[V86]].uw)106; CHECK: v0.w = vsub(v[[V84]].w,v[[V87]].w)107define <32 x i32> @f8(<32 x i32> %a0) #0 {108 %t0 = call <32 x i32> @llvm.cttz.v32i32(<32 x i32> %a0)109 ret <32 x i32> %t0110}111 112declare <128 x i8> @llvm.ctpop.v128i8(<128 x i8>) #0113declare <64 x i16> @llvm.ctpop.v64i16(<64 x i16>) #0114declare <32 x i32> @llvm.ctpop.v32i32(<32 x i32>) #0115 116declare <128 x i8> @llvm.ctlz.v128i8(<128 x i8>) #0117declare <64 x i16> @llvm.ctlz.v64i16(<64 x i16>) #0118declare <32 x i32> @llvm.ctlz.v32i32(<32 x i32>) #0119 120declare <128 x i8> @llvm.cttz.v128i8(<128 x i8>) #0121declare <64 x i16> @llvm.cttz.v64i16(<64 x i16>) #0122declare <32 x i32> @llvm.cttz.v32i32(<32 x i32>) #0123 124attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-packets" }125