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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; CHECK-LABEL: test_004; CHECK: [[R00:r[0-9]+]] = ##168430095; CHECK: [[V00:v[0-9]+]] = vsplat([[R00]])6; CHECK: v0 = vdelta(v0,[[V00]])7define <32 x i16> @test_00(<32 x i16> %a0) #0 {8 %v0 = call <32 x i16> @llvm.bswap.v32i16(<32 x i16> %a0)9 ret <32 x i16> %v010}11 12; CHECK-LABEL: test_0113; CHECK: [[R01:r[0-9]+]] = ##5052902714; CHECK: [[V01:v[0-9]+]] = vsplat([[R01]])15; CHECK: v0 = vdelta(v0,[[V01]])16define <16 x i32> @test_01(<16 x i32> %a0) #0 {17 %v0 = call <16 x i32> @llvm.bswap.v16i32(<16 x i32> %a0)18 ret <16 x i32> %v019}20 21; CHECK-LABEL: test_1022; CHECK: [[R10:r[0-9]+]] = ##1684300923; CHECK: [[V10:v[0-9]+]] = vsplat([[R10]])24; CHECK: v0 = vdelta(v0,[[V10]])25define <64 x i16> @test_10(<64 x i16> %a0) #1 {26 %v0 = call <64 x i16> @llvm.bswap.v64i16(<64 x i16> %a0)27 ret <64 x i16> %v028}29 30; CHECK-LABEL: test_1131; CHECK: [[R11:r[0-9]+]] = ##5052902732; CHECK: [[V11:v[0-9]+]] = vsplat([[R11]])33; CHECK: v0 = vdelta(v0,[[V11]])34define <32 x i32> @test_11(<32 x i32> %a0) #1 {35 %v0 = call <32 x i32> @llvm.bswap.v32i32(<32 x i32> %a0)36 ret <32 x i32> %v037}38 39declare <32 x i16> @llvm.bswap.v32i16(<32 x i16>) #040declare <16 x i32> @llvm.bswap.v16i32(<16 x i32>) #041declare <64 x i16> @llvm.bswap.v64i16(<64 x i16>) #142declare <32 x i32> @llvm.bswap.v32i32(<32 x i32>) #143 44attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }45attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }46