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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Check that vector is produced with vxor4; CHECK: v{{[0-9]*}} = vxor5define <32 x i32> @f0(i32 %x) #0 {6 %vect = insertelement <32 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 %x, i32 07 ret <32 x i32> %vect8}9 10; Check that vector is produced with vsplat11; CHECK: v{{[0-9]*}} = vsplat12define <32 x i32> @f1(i32 %x) #0 {13 %vect = insertelement <32 x i32> <i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i32 %x, i32 014 ret <32 x i32> %vect15}16 17; Check that the correct vror is generated18; CHECK: [[REG0:r([0-9]+)]] = #12019; CHECK: vror(v{{[0-9]+}},[[REG0]])20define <32 x i32> @f2(i32 %x) #0 {21 %vect = insertelement <32 x i32> <i32 1, i32 1, i32 undef, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, i32 %x, i32 222 ret <32 x i32> %vect23}24 25; Check that the correct vror is generated26; CHECK: [[REG0:r([0-9]+)]] = #1227; CHECK: vror(v{{[0-9]+}},[[REG0]])28define <32 x i32> @f3(i32 %x) #0 {29 %vect = insertelement <32 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 undef, i32 1, i32 1>, i32 %x, i32 2930 ret <32 x i32> %vect31}32 33attributes #0 = { readnone nounwind "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length128b" }34 35