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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; Check that extract-element is handled.3 4; CHECK-LABEL: ext_00:5; CHECK: r[[R000:[0-9]+]] = and(r0,#3)6; CHECK: r[[R001:[0-9]+]] = vextract(v0,r0)7; CHECK-DAG: r[[R002:[0-9]+]] = asl(r[[R000]],#3)8; CHECK-DAG: r[[R003:[0-9]+]] = #89; CHECK: r0 = extractu(r[[R001]],r[[R003]]:[[R002]])10define i8 @ext_00(<64 x i8> %a0, i32 %a1) #0 {11b2:12 %v3 = extractelement <64 x i8> %a0, i32 %a113 ret i8 %v314}15 16; CHECK-LABEL: ext_10:17; CHECK: r[[R100:[0-9]+]] = and(r0,#3)18; CHECK: r[[R101:[0-9]+]] = vextract(v0,r0)19; CHECK-DAG: r[[R102:[0-9]+]] = asl(r[[R100]],#3)20; CHECK-DAG: r[[R103:[0-9]+]] = #821; CHECK: r0 = extractu(r[[R101]],r[[R103]]:[[R102]])22define i8 @ext_10(<128 x i8> %a0, i32 %a1) #1 {23b2:24 %v3 = extractelement <128 x i8> %a0, i32 %a125 ret i8 %v326}27 28; CHECK-LABEL: ext_01:29; CHECK-DAG: r[[R010:[0-9]+]] = asl(r0,#1)30; CHECK-DAG: r[[R011:[0-9]+]] = and(r0,#1)31; CHECK-DAG: r[[R012:[0-9]+]] = #1632; CHECK: r[[R013:[0-9]+]] = asl(r[[R011]],#4)33; CHECK: r[[R014:[0-9]+]] = vextract(v0,r[[R010]])34; CHECK: r0 = extractu(r[[R014]],r[[R012]]:[[R013]])35define i16 @ext_01(<32 x i16> %a0, i32 %a1) #0 {36b2:37 %v3 = extractelement <32 x i16> %a0, i32 %a138 ret i16 %v339}40 41; CHECK-LABEL: ext_11:42; CHECK-DAG: r[[R110:[0-9]+]] = asl(r0,#1)43; CHECK-DAG: r[[R111:[0-9]+]] = and(r0,#1)44; CHECK-DAG: r[[R112:[0-9]+]] = #1645; CHECK: r[[R113:[0-9]+]] = asl(r[[R111]],#4)46; CHECK: r[[R114:[0-9]+]] = vextract(v0,r[[R110]])47; CHECK: r0 = extractu(r[[R114]],r[[R112]]:[[R113]])48define i16 @ext_11(<64 x i16> %a0, i32 %a1) #1 {49b2:50 %v3 = extractelement <64 x i16> %a0, i32 %a151 ret i16 %v352}53 54; CHECK-LABEL: ext_02:55; CHECK: [[R020:r[0-9]+]] = asl(r0,#2)56; CHECK: r0 = vextract(v0,[[R020]])57define i32 @ext_02(<16 x i32> %a0, i32 %a1) #0 {58b2:59 %v3 = extractelement <16 x i32> %a0, i32 %a160 ret i32 %v361}62 63; CHECK-LABEL: ext_12:64; CHECK: [[R120:r[0-9]+]] = asl(r0,#2)65; CHECK: r0 = vextract(v0,[[R120]])66define i32 @ext_12(<32 x i32> %a0, i32 %a1) #1 {67b2:68 %v3 = extractelement <32 x i32> %a0, i32 %a169 ret i32 %v370}71 72attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }73attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }74