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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; This testcase exposed a problem with a previous handling of selecting4; constant vectors (for vdelta). Originally a bitcast of a vsplat was5; created (both being ISD, not machine nodes). Selection of vsplat relies6; on its return type, and there was no way to get these nodes to be7; selected in the right order, without getting the main selection algorithm8; confused.9 10; Make sure this compiles successfully.11; CHECK: call f112 13target triple = "hexagon"14 15%s.0 = type { %s.1 }16%s.1 = type { i32, ptr }17%s.2 = type { i8, i8, [16 x i8], i8, [16 x i8] }18 19; Function Attrs: nounwind20define dso_local zeroext i8 @f0(i8 zeroext %a0, ptr nocapture readonly %a1, i8 signext %a2) local_unnamed_addr #0 {21b0:22 br i1 undef, label %b2, label %b123 24b1: ; preds = %b025 %v0 = load <64 x i8>, ptr undef, align 126 %v1 = icmp ult <64 x i8> %v0, <i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52>27 %v2 = xor <64 x i1> %v1, zeroinitializer28 %v3 = select <64 x i1> %v2, <64 x i32> undef, <64 x i32> zeroinitializer29 %v4 = select <64 x i1> zeroinitializer, <64 x i32> <i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000>, <64 x i32> %v330 %v5 = add <64 x i32> %v4, zeroinitializer31 br label %b232 33b2: ; preds = %b1, %b034 %v6 = phi <64 x i32> [ undef, %b0 ], [ %v5, %b1 ]35 %v7 = add <64 x i32> %v6, undef36 %v8 = add <64 x i32> %v7, undef37 %v9 = add <64 x i32> %v8, undef38 %v10 = add <64 x i32> %v9, undef39 %v11 = add <64 x i32> %v10, undef40 %v12 = add <64 x i32> %v11, undef41 %v13 = extractelement <64 x i32> %v12, i32 042 tail call void @f1(ptr null, i32 undef, i32 undef, i32 %v13, i32 undef) #243 unreachable44}45 46declare dso_local void @f1(ptr, i32, i32, i32, i32) local_unnamed_addr #147 48attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }49attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }50attributes #2 = { nounwind }51