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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define <32 x i32> @fred(i32 %a0) #0 {5; CHECK-LABEL: fred:6; CHECK: .cfi_startproc7; CHECK-NEXT: // %bb.0:8; CHECK-NEXT: {9; CHECK-NEXT: r3:2 = combine(#20,#9)10; CHECK-NEXT: v0 = vxor(v0,v0)11; CHECK-NEXT: r1 = #2412; CHECK-NEXT: r4 = #1213; CHECK-NEXT: }14; CHECK-NEXT: {15; CHECK-NEXT: v1 = vror(v0,r1)16; CHECK-NEXT: }17; CHECK-NEXT: {18; CHECK-NEXT: v1.w = vinsert(r2)19; CHECK-NEXT: r4 = #720; CHECK-NEXT: r2 = #11621; CHECK-NEXT: v0 = vror(v0,r4)22; CHECK-NEXT: }23; CHECK-NEXT: {24; CHECK-NEXT: v0.w = vinsert(r4)25; CHECK-NEXT: }26; CHECK-NEXT: {27; CHECK-NEXT: v1 = vror(v1,r3)28; CHECK-NEXT: }29; CHECK-NEXT: {30; CHECK-NEXT: v1.w = vinsert(r0)31; CHECK-NEXT: v0 = vror(v0,r2)32; CHECK-NEXT: }33; CHECK-NEXT: {34; CHECK-NEXT: v1 = vror(v1,r3)35; CHECK-NEXT: }36; CHECK-NEXT: {37; CHECK-NEXT: v0 = vor(v0,v1)38; CHECK-NEXT: jumpr r3139; CHECK-NEXT: }40 %v0 = insertelement <32 x i32> undef, i32 undef, i32 041 %v1 = insertelement <32 x i32> %v0, i32 undef, i32 142 %v2 = insertelement <32 x i32> %v1, i32 undef, i32 243 %v3 = insertelement <32 x i32> %v2, i32 7, i32 344 %v4 = insertelement <32 x i32> %v3, i32 undef, i32 445 %v5 = insertelement <32 x i32> %v4, i32 undef, i32 546 %v6 = insertelement <32 x i32> %v5, i32 undef, i32 647 %v7 = insertelement <32 x i32> %v6, i32 undef, i32 748 %v8 = insertelement <32 x i32> %v7, i32 undef, i32 849 %v9 = insertelement <32 x i32> %v8, i32 undef, i32 950 %v10 = insertelement <32 x i32> %v9, i32 undef, i32 1051 %v11 = insertelement <32 x i32> %v10, i32 undef, i32 1152 %v12 = insertelement <32 x i32> %v11, i32 undef, i32 1253 %v13 = insertelement <32 x i32> %v12, i32 undef, i32 1354 %v14 = insertelement <32 x i32> %v13, i32 undef, i32 1455 %v15 = insertelement <32 x i32> %v14, i32 undef, i32 1556 %v16 = insertelement <32 x i32> %v15, i32 undef, i32 1657 %v17 = insertelement <32 x i32> %v16, i32 undef, i32 1758 %v18 = insertelement <32 x i32> %v17, i32 undef, i32 1859 %v19 = insertelement <32 x i32> %v18, i32 undef, i32 1960 %v20 = insertelement <32 x i32> %v19, i32 undef, i32 2061 %v21 = insertelement <32 x i32> %v20, i32 undef, i32 2162 %v22 = insertelement <32 x i32> %v21, i32 9, i32 2263 %v23 = insertelement <32 x i32> %v22, i32 undef, i32 2364 %v24 = insertelement <32 x i32> %v23, i32 undef, i32 2465 %v25 = insertelement <32 x i32> %v24, i32 undef, i32 2566 %v26 = insertelement <32 x i32> %v25, i32 undef, i32 2667 %v27 = insertelement <32 x i32> %v26, i32 %a0, i32 2768 %v28 = insertelement <32 x i32> %v27, i32 undef, i32 2869 %v29 = insertelement <32 x i32> %v28, i32 undef, i32 2970 %v30 = insertelement <32 x i32> %v29, i32 undef, i32 3071 %v31 = insertelement <32 x i32> %v30, i32 undef, i32 3172 ret <32 x i32> %v3173}74 75attributes #0 = { "target-cpu"="hexagonv66" "target-features"="+hvx,+hvx-length128b" }76 77