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1; RUN: llc -mtriple=hexagon -disable-packetizer -hexagon-align-loads < %s | FileCheck %s2 3; CHECK-LABEL: test_00:4; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)5; CHECK-DAG: v[[V01:[0-9]+]] = vmem(r[[B00]]+#1)6; CHECK: valign(v[[V01]],v[[V00]],r[[B00]])7define void @test_00(ptr %p, ptr %q) #0 {8 %v0 = load <64 x i8>, ptr %p, align 19 store <64 x i8> %v0, ptr %q, align 110 ret void11}12 13; CHECK-LABEL: test_01:14; CHECK-DAG: v[[V10:[0-9]+]] = vmem(r[[B01:[0-9]+]]+#0)15; CHECK-DAG: v[[V11:[0-9]+]] = vmem(r[[B01]]+#1)16; CHECK-DAG: v[[V12:[0-9]+]] = vmem(r[[B01]]+#2)17; CHECK: }18; CHECK-DAG: valign(v[[V11]],v[[V10]],r[[B01]])19; CHECK-DAG: valign(v[[V12]],v[[V11]],r[[B01]])20define void @test_01(ptr %p, ptr %q) #0 {21 %v0 = load <128 x i8>, ptr %p, align 122 store <128 x i8> %v0, ptr %q, align 123 ret void24}25 26attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }27