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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; Check that this compiles successfully.4; CHECK: vsplat5 6target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"7target triple = "hexagon"8 9define void @fred(ptr %a0) #0 {10b0:11 %v1 = load <64 x i8>, ptr %a0, align 812 %v2 = zext <64 x i8> %v1 to <64 x i32>13 %v3 = add nuw nsw <64 x i32> %v2, zeroinitializer14 %v4 = icmp ugt <64 x i32> %v3, <i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254, i32 254>15 %v5 = zext <64 x i1> %v4 to <64 x i32>16 %v6 = add nuw nsw <64 x i32> %v3, %v517 %v7 = trunc <64 x i32> %v6 to <64 x i8>18 store <64 x i8> %v7, ptr %a0, align 819 ret void20}21 22attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }23