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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; This has a v32i8 = truncate v16i32 (64b mode), which was legalized to4; 64i8 = vpackl v32i32, for which there were no selection patterns provided.5; Check that we generate vpackeh->vpackeb for this.6 7; CHECK-LABEL: fred:8; CHECK: v[[V0:[0-9]+]].h = vpacke(v1.w,v0.w)9; CHECK: = vpacke({{.*}},v[[V0]].h)10define void @fred(ptr %a0, <32 x i32> %a1) #0 {11 %v0 = trunc <32 x i32> %a1 to <32 x i8>12 store <32 x i8> %v0, ptr %a0, align 3213 ret void14}15 16attributes #0 = { "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length64b" }17 18