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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #05declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #06declare <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1>) #07declare <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v16i1(<16 x i1>) #08declare <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1>) #09declare <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v32i1(<32 x i1>) #010 11define <16 x i32> @f0(<16 x i32> %a0, <16 x i32> %a1) #1 {12; CHECK-LABEL: f0:13; CHECK: // %bb.0: // %b014; CHECK-NEXT: {15; CHECK-NEXT: r0 = #-116; CHECK-NEXT: }17; CHECK-NEXT: {18; CHECK-NEXT: q0 = vand(v0,r0)19; CHECK-NEXT: }20; CHECK-NEXT: {21; CHECK-NEXT: q1 = vand(v1,r0)22; CHECK-NEXT: }23; CHECK-NEXT: {24; CHECK-NEXT: q0 = and(q0,q1)25; CHECK-NEXT: }26; CHECK-NEXT: {27; CHECK-NEXT: v0 = vand(q0,r0)28; CHECK-NEXT: }29; CHECK-NEXT: {30; CHECK-NEXT: jumpr r3131; CHECK-NEXT: }32b0:33 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)34 %v1 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v0)35 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)36 %v3 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v2)37 %v4 = and <16 x i1> %v1, %v338 %v5 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v16i1(<16 x i1> %v4)39 %v6 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v5, i32 -1)40 ret <16 x i32> %v641}42 43define <16 x i32> @f1(<16 x i32> %a0, <16 x i32> %a1) #1 {44; CHECK-LABEL: f1:45; CHECK: // %bb.0: // %b046; CHECK-NEXT: {47; CHECK-NEXT: r0 = #-148; CHECK-NEXT: }49; CHECK-NEXT: {50; CHECK-NEXT: q0 = vand(v0,r0)51; CHECK-NEXT: }52; CHECK-NEXT: {53; CHECK-NEXT: q1 = vand(v1,r0)54; CHECK-NEXT: }55; CHECK-NEXT: {56; CHECK-NEXT: q0 = or(q0,q1)57; CHECK-NEXT: }58; CHECK-NEXT: {59; CHECK-NEXT: v0 = vand(q0,r0)60; CHECK-NEXT: }61; CHECK-NEXT: {62; CHECK-NEXT: jumpr r3163; CHECK-NEXT: }64b0:65 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)66 %v1 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v0)67 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)68 %v3 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v2)69 %v4 = or <16 x i1> %v1, %v370 %v5 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v16i1(<16 x i1> %v4)71 %v6 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v5, i32 -1)72 ret <16 x i32> %v673}74 75define <16 x i32> @f2(<16 x i32> %a0, <16 x i32> %a1) #1 {76; CHECK-LABEL: f2:77; CHECK: // %bb.0: // %b078; CHECK-NEXT: {79; CHECK-NEXT: r0 = #-180; CHECK-NEXT: }81; CHECK-NEXT: {82; CHECK-NEXT: q0 = vand(v0,r0)83; CHECK-NEXT: }84; CHECK-NEXT: {85; CHECK-NEXT: q1 = vand(v1,r0)86; CHECK-NEXT: }87; CHECK-NEXT: {88; CHECK-NEXT: q0 = xor(q0,q1)89; CHECK-NEXT: }90; CHECK-NEXT: {91; CHECK-NEXT: v0 = vand(q0,r0)92; CHECK-NEXT: }93; CHECK-NEXT: {94; CHECK-NEXT: jumpr r3195; CHECK-NEXT: }96b0:97 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)98 %v1 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v0)99 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)100 %v3 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v2)101 %v4 = xor <16 x i1> %v1, %v3102 %v5 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v16i1(<16 x i1> %v4)103 %v6 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v5, i32 -1)104 ret <16 x i32> %v6105}106 107define <16 x i32> @f3(<16 x i32> %a0, <16 x i32> %a1) #1 {108; CHECK-LABEL: f3:109; CHECK: // %bb.0: // %b0110; CHECK-NEXT: {111; CHECK-NEXT: r0 = #-1112; CHECK-NEXT: }113; CHECK-NEXT: {114; CHECK-NEXT: q0 = vand(v0,r0)115; CHECK-NEXT: }116; CHECK-NEXT: {117; CHECK-NEXT: q1 = vand(v1,r0)118; CHECK-NEXT: }119; CHECK-NEXT: {120; CHECK-NEXT: q0 = and(q0,!q1)121; CHECK-NEXT: }122; CHECK-NEXT: {123; CHECK-NEXT: v0 = vand(q0,r0)124; CHECK-NEXT: }125; CHECK-NEXT: {126; CHECK-NEXT: jumpr r31127; CHECK-NEXT: }128b0:129 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)130 %v1 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v0)131 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)132 %v3 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v2)133 %v4 = xor <16 x i1> %v3, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>134 %v5 = and <16 x i1> %v1, %v4135 %v6 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v16i1(<16 x i1> %v5)136 %v7 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v6, i32 -1)137 ret <16 x i32> %v7138}139 140define <16 x i32> @f4(<16 x i32> %a0, <16 x i32> %a1) #1 {141; CHECK-LABEL: f4:142; CHECK: // %bb.0: // %b0143; CHECK-NEXT: {144; CHECK-NEXT: r0 = #-1145; CHECK-NEXT: }146; CHECK-NEXT: {147; CHECK-NEXT: q0 = vand(v0,r0)148; CHECK-NEXT: }149; CHECK-NEXT: {150; CHECK-NEXT: q1 = vand(v1,r0)151; CHECK-NEXT: }152; CHECK-NEXT: {153; CHECK-NEXT: q0 = or(q0,!q1)154; CHECK-NEXT: }155; CHECK-NEXT: {156; CHECK-NEXT: v0 = vand(q0,r0)157; CHECK-NEXT: }158; CHECK-NEXT: {159; CHECK-NEXT: jumpr r31160; CHECK-NEXT: }161b0:162 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)163 %v1 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v0)164 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)165 %v3 = call <16 x i1> @llvm.hexagon.V6.pred.typecast.v16i1.v64i1(<64 x i1> %v2)166 %v4 = xor <16 x i1> %v3, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>167 %v5 = or <16 x i1> %v1, %v4168 %v6 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v16i1(<16 x i1> %v5)169 %v7 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v6, i32 -1)170 ret <16 x i32> %v7171}172 173define <16 x i32> @f5(<16 x i32> %a0, <16 x i32> %a1) #1 {174; CHECK-LABEL: f5:175; CHECK: // %bb.0: // %b0176; CHECK-NEXT: {177; CHECK-NEXT: r0 = #-1178; CHECK-NEXT: }179; CHECK-NEXT: {180; CHECK-NEXT: q0 = vand(v0,r0)181; CHECK-NEXT: }182; CHECK-NEXT: {183; CHECK-NEXT: q1 = vand(v1,r0)184; CHECK-NEXT: }185; CHECK-NEXT: {186; CHECK-NEXT: q0 = and(q0,q1)187; CHECK-NEXT: }188; CHECK-NEXT: {189; CHECK-NEXT: v0 = vand(q0,r0)190; CHECK-NEXT: }191; CHECK-NEXT: {192; CHECK-NEXT: jumpr r31193; CHECK-NEXT: }194b0:195 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)196 %v1 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v0)197 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)198 %v3 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v2)199 %v4 = and <32 x i1> %v1, %v3200 %v5 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v32i1(<32 x i1> %v4)201 %v6 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v5, i32 -1)202 ret <16 x i32> %v6203}204 205define <16 x i32> @f6(<16 x i32> %a0, <16 x i32> %a1) #1 {206; CHECK-LABEL: f6:207; CHECK: // %bb.0: // %b0208; CHECK-NEXT: {209; CHECK-NEXT: r0 = #-1210; CHECK-NEXT: }211; CHECK-NEXT: {212; CHECK-NEXT: q0 = vand(v0,r0)213; CHECK-NEXT: }214; CHECK-NEXT: {215; CHECK-NEXT: q1 = vand(v1,r0)216; CHECK-NEXT: }217; CHECK-NEXT: {218; CHECK-NEXT: q0 = or(q0,q1)219; CHECK-NEXT: }220; CHECK-NEXT: {221; CHECK-NEXT: v0 = vand(q0,r0)222; CHECK-NEXT: }223; CHECK-NEXT: {224; CHECK-NEXT: jumpr r31225; CHECK-NEXT: }226b0:227 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)228 %v1 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v0)229 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)230 %v3 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v2)231 %v4 = or <32 x i1> %v1, %v3232 %v5 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v32i1(<32 x i1> %v4)233 %v6 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v5, i32 -1)234 ret <16 x i32> %v6235}236 237define <16 x i32> @f7(<16 x i32> %a0, <16 x i32> %a1) #1 {238; CHECK-LABEL: f7:239; CHECK: // %bb.0: // %b0240; CHECK-NEXT: {241; CHECK-NEXT: r0 = #-1242; CHECK-NEXT: }243; CHECK-NEXT: {244; CHECK-NEXT: q0 = vand(v0,r0)245; CHECK-NEXT: }246; CHECK-NEXT: {247; CHECK-NEXT: q1 = vand(v1,r0)248; CHECK-NEXT: }249; CHECK-NEXT: {250; CHECK-NEXT: q0 = xor(q0,q1)251; CHECK-NEXT: }252; CHECK-NEXT: {253; CHECK-NEXT: v0 = vand(q0,r0)254; CHECK-NEXT: }255; CHECK-NEXT: {256; CHECK-NEXT: jumpr r31257; CHECK-NEXT: }258b0:259 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)260 %v1 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v0)261 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)262 %v3 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v2)263 %v4 = xor <32 x i1> %v1, %v3264 %v5 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v32i1(<32 x i1> %v4)265 %v6 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v5, i32 -1)266 ret <16 x i32> %v6267}268 269define <16 x i32> @f8(<16 x i32> %a0, <16 x i32> %a1) #1 {270; CHECK-LABEL: f8:271; CHECK: // %bb.0: // %b0272; CHECK-NEXT: {273; CHECK-NEXT: r0 = #-1274; CHECK-NEXT: }275; CHECK-NEXT: {276; CHECK-NEXT: q0 = vand(v0,r0)277; CHECK-NEXT: }278; CHECK-NEXT: {279; CHECK-NEXT: q1 = vand(v1,r0)280; CHECK-NEXT: }281; CHECK-NEXT: {282; CHECK-NEXT: q0 = and(q0,!q1)283; CHECK-NEXT: }284; CHECK-NEXT: {285; CHECK-NEXT: v0 = vand(q0,r0)286; CHECK-NEXT: }287; CHECK-NEXT: {288; CHECK-NEXT: jumpr r31289; CHECK-NEXT: }290b0:291 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)292 %v1 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v0)293 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)294 %v3 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v2)295 %v4 = xor <32 x i1> %v3, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>296 %v5 = and <32 x i1> %v1, %v4297 %v6 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v32i1(<32 x i1> %v5)298 %v7 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v6, i32 -1)299 ret <16 x i32> %v7300}301 302define <16 x i32> @f9(<16 x i32> %a0, <16 x i32> %a1) #1 {303; CHECK-LABEL: f9:304; CHECK: // %bb.0: // %b0305; CHECK-NEXT: {306; CHECK-NEXT: r0 = #-1307; CHECK-NEXT: }308; CHECK-NEXT: {309; CHECK-NEXT: q0 = vand(v0,r0)310; CHECK-NEXT: }311; CHECK-NEXT: {312; CHECK-NEXT: q1 = vand(v1,r0)313; CHECK-NEXT: }314; CHECK-NEXT: {315; CHECK-NEXT: q0 = or(q0,!q1)316; CHECK-NEXT: }317; CHECK-NEXT: {318; CHECK-NEXT: v0 = vand(q0,r0)319; CHECK-NEXT: }320; CHECK-NEXT: {321; CHECK-NEXT: jumpr r31322; CHECK-NEXT: }323b0:324 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)325 %v1 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v0)326 %v2 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)327 %v3 = call <32 x i1> @llvm.hexagon.V6.pred.typecast.v32i1.v64i1(<64 x i1> %v2)328 %v4 = xor <32 x i1> %v3, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>329 %v5 = or <32 x i1> %v1, %v4330 %v6 = call <64 x i1> @llvm.hexagon.V6.pred.typecast.v64i1.v32i1(<32 x i1> %v5)331 %v7 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v6, i32 -1)332 ret <16 x i32> %v7333}334 335define <16 x i32> @f10(<16 x i32> %a0, <16 x i32> %a1) #1 {336; CHECK-LABEL: f10:337; CHECK: // %bb.0: // %b0338; CHECK-NEXT: {339; CHECK-NEXT: r0 = #-1340; CHECK-NEXT: }341; CHECK-NEXT: {342; CHECK-NEXT: q0 = vand(v0,r0)343; CHECK-NEXT: }344; CHECK-NEXT: {345; CHECK-NEXT: q1 = vand(v1,r0)346; CHECK-NEXT: }347; CHECK-NEXT: {348; CHECK-NEXT: q0 = and(q0,q1)349; CHECK-NEXT: }350; CHECK-NEXT: {351; CHECK-NEXT: v0 = vand(q0,r0)352; CHECK-NEXT: }353; CHECK-NEXT: {354; CHECK-NEXT: jumpr r31355; CHECK-NEXT: }356b0:357 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)358 %v1 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)359 %v2 = and <64 x i1> %v0, %v1360 %v3 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v2, i32 -1)361 ret <16 x i32> %v3362}363 364define <16 x i32> @f11(<16 x i32> %a0, <16 x i32> %a1) #1 {365; CHECK-LABEL: f11:366; CHECK: // %bb.0: // %b0367; CHECK-NEXT: {368; CHECK-NEXT: r0 = #-1369; CHECK-NEXT: }370; CHECK-NEXT: {371; CHECK-NEXT: q0 = vand(v0,r0)372; CHECK-NEXT: }373; CHECK-NEXT: {374; CHECK-NEXT: q1 = vand(v1,r0)375; CHECK-NEXT: }376; CHECK-NEXT: {377; CHECK-NEXT: q0 = or(q0,q1)378; CHECK-NEXT: }379; CHECK-NEXT: {380; CHECK-NEXT: v0 = vand(q0,r0)381; CHECK-NEXT: }382; CHECK-NEXT: {383; CHECK-NEXT: jumpr r31384; CHECK-NEXT: }385b0:386 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)387 %v1 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)388 %v2 = or <64 x i1> %v0, %v1389 %v3 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v2, i32 -1)390 ret <16 x i32> %v3391}392 393define <16 x i32> @f12(<16 x i32> %a0, <16 x i32> %a1) #1 {394; CHECK-LABEL: f12:395; CHECK: // %bb.0: // %b0396; CHECK-NEXT: {397; CHECK-NEXT: r0 = #-1398; CHECK-NEXT: }399; CHECK-NEXT: {400; CHECK-NEXT: q0 = vand(v0,r0)401; CHECK-NEXT: }402; CHECK-NEXT: {403; CHECK-NEXT: q1 = vand(v1,r0)404; CHECK-NEXT: }405; CHECK-NEXT: {406; CHECK-NEXT: q0 = xor(q0,q1)407; CHECK-NEXT: }408; CHECK-NEXT: {409; CHECK-NEXT: v0 = vand(q0,r0)410; CHECK-NEXT: }411; CHECK-NEXT: {412; CHECK-NEXT: jumpr r31413; CHECK-NEXT: }414b0:415 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)416 %v1 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)417 %v2 = xor <64 x i1> %v0, %v1418 %v3 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v2, i32 -1)419 ret <16 x i32> %v3420}421 422define <16 x i32> @f13(<16 x i32> %a0, <16 x i32> %a1) #1 {423; CHECK-LABEL: f13:424; CHECK: // %bb.0: // %b0425; CHECK-NEXT: {426; CHECK-NEXT: r0 = #-1427; CHECK-NEXT: }428; CHECK-NEXT: {429; CHECK-NEXT: q0 = vand(v0,r0)430; CHECK-NEXT: }431; CHECK-NEXT: {432; CHECK-NEXT: q1 = vand(v1,r0)433; CHECK-NEXT: }434; CHECK-NEXT: {435; CHECK-NEXT: q0 = and(q0,!q1)436; CHECK-NEXT: }437; CHECK-NEXT: {438; CHECK-NEXT: v0 = vand(q0,r0)439; CHECK-NEXT: }440; CHECK-NEXT: {441; CHECK-NEXT: jumpr r31442; CHECK-NEXT: }443b0:444 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)445 %v1 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)446 %v2 = xor <64 x i1> %v1, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>447 %v3 = and <64 x i1> %v0, %v2448 %v4 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v3, i32 -1)449 ret <16 x i32> %v4450}451 452define <16 x i32> @f14(<16 x i32> %a0, <16 x i32> %a1) #1 {453; CHECK-LABEL: f14:454; CHECK: // %bb.0: // %b0455; CHECK-NEXT: {456; CHECK-NEXT: r0 = #-1457; CHECK-NEXT: }458; CHECK-NEXT: {459; CHECK-NEXT: q0 = vand(v0,r0)460; CHECK-NEXT: }461; CHECK-NEXT: {462; CHECK-NEXT: q1 = vand(v1,r0)463; CHECK-NEXT: }464; CHECK-NEXT: {465; CHECK-NEXT: q0 = or(q0,!q1)466; CHECK-NEXT: }467; CHECK-NEXT: {468; CHECK-NEXT: v0 = vand(q0,r0)469; CHECK-NEXT: }470; CHECK-NEXT: {471; CHECK-NEXT: jumpr r31472; CHECK-NEXT: }473b0:474 %v0 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a0, i32 -1)475 %v1 = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %a1, i32 -1)476 %v2 = xor <64 x i1> %v1, <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>477 %v3 = or <64 x i1> %v0, %v2478 %v4 = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v3, i32 -1)479 ret <16 x i32> %v4480}481 482attributes #0 = { nounwind readnone }483attributes #1 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length64b,-packets" }484