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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-qfloat < %s | FileCheck %s3; RUN: llc -mtriple=hexagon -mattr=+hvxv69,+hvx-length128b,+hvx-ieee-fp < %s | FileCheck %s4 5; min6 7define <64 x half> @test_00(<64 x half> %v0, <64 x half> %v1) #0 {8; CHECK-LABEL: test_00:9; CHECK:       // %bb.0:10; CHECK-NEXT:    {11; CHECK-NEXT:     v0.hf = vmin(v1.hf,v0.hf)12; CHECK-NEXT:     jumpr r3113; CHECK-NEXT:    }14  %t0 = fcmp olt <64 x half> %v0, %v115  %t1 = select <64 x i1> %t0, <64 x half> %v0, <64 x half> %v116  ret <64 x half> %t117}18 19define <64 x half> @test_01(<64 x half> %v0, <64 x half> %v1) #0 {20; CHECK-LABEL: test_01:21; CHECK:       // %bb.0:22; CHECK-NEXT:    {23; CHECK-NEXT:     q0 = vcmp.gt(v0.hf,v1.hf)24; CHECK-NEXT:    }25; CHECK-NEXT:    {26; CHECK-NEXT:     v0 = vmux(q0,v1,v0)27; CHECK-NEXT:     jumpr r3128; CHECK-NEXT:    }29  %t0 = fcmp ole <64 x half> %v0, %v130  %t1 = select <64 x i1> %t0, <64 x half> %v0, <64 x half> %v131  ret <64 x half> %t132}33 34define <64 x half> @test_02(<64 x half> %v0, <64 x half> %v1) #0 {35; CHECK-LABEL: test_02:36; CHECK:       // %bb.0:37; CHECK-NEXT:    {38; CHECK-NEXT:     v0.hf = vmin(v0.hf,v1.hf)39; CHECK-NEXT:     jumpr r3140; CHECK-NEXT:    }41  %t0 = fcmp ogt <64 x half> %v0, %v142  %t1 = select <64 x i1> %t0, <64 x half> %v1, <64 x half> %v043  ret <64 x half> %t144}45 46define <64 x half> @test_03(<64 x half> %v0, <64 x half> %v1) #0 {47; CHECK-LABEL: test_03:48; CHECK:       // %bb.0:49; CHECK-NEXT:    {50; CHECK-NEXT:     q0 = vcmp.gt(v1.hf,v0.hf)51; CHECK-NEXT:    }52; CHECK-NEXT:    {53; CHECK-NEXT:     v0 = vmux(q0,v0,v1)54; CHECK-NEXT:     jumpr r3155; CHECK-NEXT:    }56  %t0 = fcmp oge <64 x half> %v0, %v157  %t1 = select <64 x i1> %t0, <64 x half> %v1, <64 x half> %v058  ret <64 x half> %t159}60 61define <32 x float> @test_10(<32 x float> %v0, <32 x float> %v1) #0 {62; CHECK-LABEL: test_10:63; CHECK:       // %bb.0:64; CHECK-NEXT:    {65; CHECK-NEXT:     v0.sf = vmin(v1.sf,v0.sf)66; CHECK-NEXT:     jumpr r3167; CHECK-NEXT:    }68  %t0 = fcmp olt <32 x float> %v0, %v169  %t1 = select <32 x i1> %t0, <32 x float> %v0, <32 x float> %v170  ret <32 x float> %t171}72 73define <32 x float> @test_11(<32 x float> %v0, <32 x float> %v1) #0 {74; CHECK-LABEL: test_11:75; CHECK:       // %bb.0:76; CHECK-NEXT:    {77; CHECK-NEXT:     q0 = vcmp.gt(v0.sf,v1.sf)78; CHECK-NEXT:    }79; CHECK-NEXT:    {80; CHECK-NEXT:     v0 = vmux(q0,v1,v0)81; CHECK-NEXT:     jumpr r3182; CHECK-NEXT:    }83  %t0 = fcmp ole <32 x float> %v0, %v184  %t1 = select <32 x i1> %t0, <32 x float> %v0, <32 x float> %v185  ret <32 x float> %t186}87 88define <32 x float> @test_12(<32 x float> %v0, <32 x float> %v1) #0 {89; CHECK-LABEL: test_12:90; CHECK:       // %bb.0:91; CHECK-NEXT:    {92; CHECK-NEXT:     v0.sf = vmin(v0.sf,v1.sf)93; CHECK-NEXT:     jumpr r3194; CHECK-NEXT:    }95  %t0 = fcmp ogt <32 x float> %v0, %v196  %t1 = select <32 x i1> %t0, <32 x float> %v1, <32 x float> %v097  ret <32 x float> %t198}99 100define <32 x float> @test_13(<32 x float> %v0, <32 x float> %v1) #0 {101; CHECK-LABEL: test_13:102; CHECK:       // %bb.0:103; CHECK-NEXT:    {104; CHECK-NEXT:     q0 = vcmp.gt(v1.sf,v0.sf)105; CHECK-NEXT:    }106; CHECK-NEXT:    {107; CHECK-NEXT:     v0 = vmux(q0,v0,v1)108; CHECK-NEXT:     jumpr r31109; CHECK-NEXT:    }110  %t0 = fcmp oge <32 x float> %v0, %v1111  %t1 = select <32 x i1> %t0, <32 x float> %v1, <32 x float> %v0112  ret <32 x float> %t1113}114 115; max116 117define <64 x half> @test_20(<64 x half> %v0, <64 x half> %v1) #0 {118; CHECK-LABEL: test_20:119; CHECK:       // %bb.0:120; CHECK-NEXT:    {121; CHECK-NEXT:     v0.hf = vmax(v1.hf,v0.hf)122; CHECK-NEXT:     jumpr r31123; CHECK-NEXT:    }124  %t0 = fcmp olt <64 x half> %v0, %v1125  %t1 = select <64 x i1> %t0, <64 x half> %v1, <64 x half> %v0126  ret <64 x half> %t1127}128 129define <64 x half> @test_21(<64 x half> %v0, <64 x half> %v1) #0 {130; CHECK-LABEL: test_21:131; CHECK:       // %bb.0:132; CHECK-NEXT:    {133; CHECK-NEXT:     q0 = vcmp.gt(v0.hf,v1.hf)134; CHECK-NEXT:    }135; CHECK-NEXT:    {136; CHECK-NEXT:     v0 = vmux(q0,v0,v1)137; CHECK-NEXT:     jumpr r31138; CHECK-NEXT:    }139  %t0 = fcmp ole <64 x half> %v0, %v1140  %t1 = select <64 x i1> %t0, <64 x half> %v1, <64 x half> %v0141  ret <64 x half> %t1142}143 144define <64 x half> @test_22(<64 x half> %v0, <64 x half> %v1) #0 {145; CHECK-LABEL: test_22:146; CHECK:       // %bb.0:147; CHECK-NEXT:    {148; CHECK-NEXT:     v0.hf = vmax(v0.hf,v1.hf)149; CHECK-NEXT:     jumpr r31150; CHECK-NEXT:    }151  %t0 = fcmp ogt <64 x half> %v0, %v1152  %t1 = select <64 x i1> %t0, <64 x half> %v0, <64 x half> %v1153  ret <64 x half> %t1154}155 156define <64 x half> @test_23(<64 x half> %v0, <64 x half> %v1) #0 {157; CHECK-LABEL: test_23:158; CHECK:       // %bb.0:159; CHECK-NEXT:    {160; CHECK-NEXT:     q0 = vcmp.gt(v1.hf,v0.hf)161; CHECK-NEXT:    }162; CHECK-NEXT:    {163; CHECK-NEXT:     v0 = vmux(q0,v1,v0)164; CHECK-NEXT:     jumpr r31165; CHECK-NEXT:    }166  %t0 = fcmp oge <64 x half> %v0, %v1167  %t1 = select <64 x i1> %t0, <64 x half> %v0, <64 x half> %v1168  ret <64 x half> %t1169}170 171define <32 x float> @test_30(<32 x float> %v0, <32 x float> %v1) #0 {172; CHECK-LABEL: test_30:173; CHECK:       // %bb.0:174; CHECK-NEXT:    {175; CHECK-NEXT:     v0.sf = vmax(v1.sf,v0.sf)176; CHECK-NEXT:     jumpr r31177; CHECK-NEXT:    }178  %t0 = fcmp olt <32 x float> %v0, %v1179  %t1 = select <32 x i1> %t0, <32 x float> %v1, <32 x float> %v0180  ret <32 x float> %t1181}182 183define <32 x float> @test_31(<32 x float> %v0, <32 x float> %v1) #0 {184; CHECK-LABEL: test_31:185; CHECK:       // %bb.0:186; CHECK-NEXT:    {187; CHECK-NEXT:     q0 = vcmp.gt(v0.sf,v1.sf)188; CHECK-NEXT:    }189; CHECK-NEXT:    {190; CHECK-NEXT:     v0 = vmux(q0,v0,v1)191; CHECK-NEXT:     jumpr r31192; CHECK-NEXT:    }193  %t0 = fcmp ole <32 x float> %v0, %v1194  %t1 = select <32 x i1> %t0, <32 x float> %v1, <32 x float> %v0195  ret <32 x float> %t1196}197 198define <32 x float> @test_32(<32 x float> %v0, <32 x float> %v1) #0 {199; CHECK-LABEL: test_32:200; CHECK:       // %bb.0:201; CHECK-NEXT:    {202; CHECK-NEXT:     v0.sf = vmax(v0.sf,v1.sf)203; CHECK-NEXT:     jumpr r31204; CHECK-NEXT:    }205  %t0 = fcmp ogt <32 x float> %v0, %v1206  %t1 = select <32 x i1> %t0, <32 x float> %v0, <32 x float> %v1207  ret <32 x float> %t1208}209 210define <32 x float> @test_33(<32 x float> %v0, <32 x float> %v1) #0 {211; CHECK-LABEL: test_33:212; CHECK:       // %bb.0:213; CHECK-NEXT:    {214; CHECK-NEXT:     q0 = vcmp.gt(v1.sf,v0.sf)215; CHECK-NEXT:    }216; CHECK-NEXT:    {217; CHECK-NEXT:     v0 = vmux(q0,v1,v0)218; CHECK-NEXT:     jumpr r31219; CHECK-NEXT:    }220  %t0 = fcmp oge <32 x float> %v0, %v1221  %t1 = select <32 x i1> %t0, <32 x float> %v0, <32 x float> %v1222  ret <32 x float> %t1223}224 225attributes #0 = { readnone nounwind "target-cpu"="hexagonv69" }226 227