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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define void @f0(ptr %a0, ptr %a1, ptr %a2) #0 {5; CHECK-LABEL: f0:6; CHECK: // %bb.0: // %b07; CHECK-NEXT: {8; CHECK-NEXT: v0 = vmem(r0+#0)9; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: v1 = vmem(r1+#0)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: v2.w = vmpye(v0.w,v1.uh)15; CHECK-NEXT: }16; CHECK-NEXT: {17; CHECK-NEXT: v2.w += vmpyo(v0.w,v1.h):<<1:sat:shift18; CHECK-NEXT: }19; CHECK-NEXT: {20; CHECK-NEXT: vmem(r2+#0) = v221; CHECK-NEXT: }22; CHECK-NEXT: {23; CHECK-NEXT: jumpr r3124; CHECK-NEXT: }25b0:26 %v0 = load <32 x i32>, ptr %a0, align 12827 %v1 = load <32 x i32>, ptr %a1, align 12828 %v2 = sext <32 x i32> %v0 to <32 x i64>29 %v3 = sext <32 x i32> %v1 to <32 x i64>30 %v4 = mul nsw <32 x i64> %v2, %v331 %v5 = lshr <32 x i64> %v4, <i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31>32 %v6 = trunc <32 x i64> %v5 to <32 x i32>33 store <32 x i32> %v6, ptr %a2, align 12834 ret void35}36 37define void @f1(ptr %a0, ptr %a1, ptr %a2) #0 {38; CHECK-LABEL: f1:39; CHECK: // %bb.0: // %b040; CHECK-NEXT: {41; CHECK-NEXT: v0 = vmem(r0+#0)42; CHECK-NEXT: }43; CHECK-NEXT: {44; CHECK-NEXT: v1 = vmem(r1+#0)45; CHECK-NEXT: }46; CHECK-NEXT: {47; CHECK-NEXT: v2.w = vmpye(v0.w,v1.uh)48; CHECK-NEXT: }49; CHECK-NEXT: {50; CHECK-NEXT: v2.w += vmpyo(v0.w,v1.h):<<1:rnd:sat:shift51; CHECK-NEXT: }52; CHECK-NEXT: {53; CHECK-NEXT: vmem(r2+#0) = v254; CHECK-NEXT: }55; CHECK-NEXT: {56; CHECK-NEXT: jumpr r3157; CHECK-NEXT: }58b0:59 %v0 = load <32 x i32>, ptr %a0, align 12860 %v1 = load <32 x i32>, ptr %a1, align 12861 %v2 = sext <32 x i32> %v0 to <32 x i64>62 %v3 = sext <32 x i32> %v1 to <32 x i64>63 %v4 = mul nsw <32 x i64> %v2, %v364 %v5 = add nsw <32 x i64> %v4, <i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824, i64 1073741824>65 %v6 = lshr <32 x i64> %v5, <i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31, i64 31>66 %v7 = trunc <32 x i64> %v6 to <32 x i32>67 store <32 x i32> %v7, ptr %a2, align 12868 ret void69}70 71define void @f2(ptr %a0, ptr %a1, ptr %a2) #0 {72; CHECK-LABEL: f2:73; CHECK: // %bb.0: // %b074; CHECK-NEXT: {75; CHECK-NEXT: v0 = vmem(r1+#0)76; CHECK-NEXT: }77; CHECK-NEXT: {78; CHECK-NEXT: r7 = #-479; CHECK-NEXT: }80; CHECK-NEXT: {81; CHECK-NEXT: r3 = #1582; CHECK-NEXT: }83; CHECK-NEXT: {84; CHECK-NEXT: v1 = vmem(r0+#0)85; CHECK-NEXT: }86; CHECK-NEXT: {87; CHECK-NEXT: v1:0.w = vmpy(v0.h,v1.h)88; CHECK-NEXT: }89; CHECK-NEXT: {90; CHECK-NEXT: v1:0 = vshuff(v1,v0,r7)91; CHECK-NEXT: }92; CHECK-NEXT: {93; CHECK-NEXT: v0.uw = vlsr(v0.uw,r3)94; CHECK-NEXT: }95; CHECK-NEXT: {96; CHECK-NEXT: v1.uw = vlsr(v1.uw,r3)97; CHECK-NEXT: }98; CHECK-NEXT: {99; CHECK-NEXT: v0.h = vpacke(v1.w,v0.w)100; CHECK-NEXT: }101; CHECK-NEXT: {102; CHECK-NEXT: vmem(r2+#0) = v0103; CHECK-NEXT: }104; CHECK-NEXT: {105; CHECK-NEXT: jumpr r31106; CHECK-NEXT: }107b0:108 %v0 = load <64 x i16>, ptr %a0, align 128109 %v1 = load <64 x i16>, ptr %a1, align 128110 %v2 = sext <64 x i16> %v0 to <64 x i32>111 %v3 = sext <64 x i16> %v1 to <64 x i32>112 %v4 = mul nsw <64 x i32> %v2, %v3113 %v5 = lshr <64 x i32> %v4, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>114 %v6 = trunc <64 x i32> %v5 to <64 x i16>115 store <64 x i16> %v6, ptr %a2, align 128116 ret void117}118 119define void @f3(ptr %a0, ptr %a1, ptr %a2) #0 {120; CHECK-LABEL: f3:121; CHECK: // %bb.0: // %b0122; CHECK-NEXT: {123; CHECK-NEXT: v0 = vmem(r0+#0)124; CHECK-NEXT: }125; CHECK-NEXT: {126; CHECK-NEXT: v1 = vmem(r1+#0)127; CHECK-NEXT: }128; CHECK-NEXT: {129; CHECK-NEXT: v0.h = vmpy(v0.h,v1.h):<<1:rnd:sat130; CHECK-NEXT: }131; CHECK-NEXT: {132; CHECK-NEXT: vmem(r2+#0) = v0133; CHECK-NEXT: }134; CHECK-NEXT: {135; CHECK-NEXT: jumpr r31136; CHECK-NEXT: }137b0:138 %v0 = load <64 x i16>, ptr %a0, align 128139 %v1 = load <64 x i16>, ptr %a1, align 128140 %v2 = sext <64 x i16> %v0 to <64 x i32>141 %v3 = sext <64 x i16> %v1 to <64 x i32>142 %v4 = mul nsw <64 x i32> %v2, %v3143 %v5 = add nsw <64 x i32> %v4, <i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384, i32 16384>144 %v6 = lshr <64 x i32> %v5, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>145 %v7 = trunc <64 x i32> %v6 to <64 x i16>146 store <64 x i16> %v7, ptr %a2, align 128147 ret void148}149 150attributes #0 = { nounwind "target-features"="+v68,+hvxv68,+hvx-length128b,-packets" }151