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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define <128 x i8> @test0000(<128 x i8> %a0, i8 %a1) #0 {5; CHECK-LABEL: test0000:6; CHECK: // %bb.0:7; CHECK-NEXT: {8; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)9; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: v0.h = vasl(v0.h,r0)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: v1.h = vasl(v1.h,r0)15; CHECK-NEXT: }16; CHECK-NEXT: {17; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)18; CHECK-NEXT: jumpr r3119; CHECK-NEXT: }20 %b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 021 %b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer22 %v0 = shl <128 x i8> %a0, %b123 ret <128 x i8> %v024}25 26define <128 x i8> @test0001(<128 x i8> %a0, i8 %a1) #0 {27; CHECK-LABEL: test0001:28; CHECK: // %bb.0:29; CHECK-NEXT: {30; CHECK-NEXT: v1:0.h = vsxt(v0.b)31; CHECK-NEXT: }32; CHECK-NEXT: {33; CHECK-NEXT: v0.h = vasr(v0.h,r0)34; CHECK-NEXT: }35; CHECK-NEXT: {36; CHECK-NEXT: v1.h = vasr(v1.h,r0)37; CHECK-NEXT: }38; CHECK-NEXT: {39; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)40; CHECK-NEXT: jumpr r3141; CHECK-NEXT: }42 %b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 043 %b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer44 %v0 = ashr <128 x i8> %a0, %b145 ret <128 x i8> %v046}47 48define <128 x i8> @test0002(<128 x i8> %a0, i8 %a1) #0 {49; CHECK-LABEL: test0002:50; CHECK: // %bb.0:51; CHECK-NEXT: {52; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)53; CHECK-NEXT: }54; CHECK-NEXT: {55; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)56; CHECK-NEXT: }57; CHECK-NEXT: {58; CHECK-NEXT: v1.uh = vlsr(v1.uh,r0)59; CHECK-NEXT: }60; CHECK-NEXT: {61; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)62; CHECK-NEXT: jumpr r3163; CHECK-NEXT: }64 %b0 = insertelement <128 x i8> zeroinitializer, i8 %a1, i32 065 %b1 = shufflevector <128 x i8> %b0, <128 x i8> undef, <128 x i32> zeroinitializer66 %v0 = lshr <128 x i8> %a0, %b167 ret <128 x i8> %v068}69 70define <64 x i16> @test0010(<64 x i16> %a0, i16 %a1) #0 {71; CHECK-LABEL: test0010:72; CHECK: // %bb.0:73; CHECK-NEXT: {74; CHECK-NEXT: v0.h = vasl(v0.h,r0)75; CHECK-NEXT: jumpr r3176; CHECK-NEXT: }77 %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 078 %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer79 %v0 = shl <64 x i16> %a0, %b180 ret <64 x i16> %v081}82 83define <64 x i16> @test0011(<64 x i16> %a0, i16 %a1) #0 {84; CHECK-LABEL: test0011:85; CHECK: // %bb.0:86; CHECK-NEXT: {87; CHECK-NEXT: v0.h = vasr(v0.h,r0)88; CHECK-NEXT: jumpr r3189; CHECK-NEXT: }90 %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 091 %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer92 %v0 = ashr <64 x i16> %a0, %b193 ret <64 x i16> %v094}95 96define <64 x i16> @test0012(<64 x i16> %a0, i16 %a1) #0 {97; CHECK-LABEL: test0012:98; CHECK: // %bb.0:99; CHECK-NEXT: {100; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)101; CHECK-NEXT: jumpr r31102; CHECK-NEXT: }103 %b0 = insertelement <64 x i16> zeroinitializer, i16 %a1, i32 0104 %b1 = shufflevector <64 x i16> %b0, <64 x i16> undef, <64 x i32> zeroinitializer105 %v0 = lshr <64 x i16> %a0, %b1106 ret <64 x i16> %v0107}108 109define <32 x i32> @test0020(<32 x i32> %a0, i32 %a1) #0 {110; CHECK-LABEL: test0020:111; CHECK: // %bb.0:112; CHECK-NEXT: {113; CHECK-NEXT: v0.w = vasl(v0.w,r0)114; CHECK-NEXT: jumpr r31115; CHECK-NEXT: }116 %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0117 %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer118 %v0 = shl <32 x i32> %a0, %b1119 ret <32 x i32> %v0120}121 122define <32 x i32> @test0021(<32 x i32> %a0, i32 %a1) #0 {123; CHECK-LABEL: test0021:124; CHECK: // %bb.0:125; CHECK-NEXT: {126; CHECK-NEXT: v0.w = vasr(v0.w,r0)127; CHECK-NEXT: jumpr r31128; CHECK-NEXT: }129 %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0130 %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer131 %v0 = ashr <32 x i32> %a0, %b1132 ret <32 x i32> %v0133}134 135define <32 x i32> @test0022(<32 x i32> %a0, i32 %a1) #0 {136; CHECK-LABEL: test0022:137; CHECK: // %bb.0:138; CHECK-NEXT: {139; CHECK-NEXT: v0.uw = vlsr(v0.uw,r0)140; CHECK-NEXT: jumpr r31141; CHECK-NEXT: }142 %b0 = insertelement <32 x i32> zeroinitializer, i32 %a1, i32 0143 %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer144 %v0 = lshr <32 x i32> %a0, %b1145 ret <32 x i32> %v0146}147 148define <32 x i32> @test0023(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {149; CHECK-LABEL: test0023:150; CHECK: // %bb.0:151; CHECK-NEXT: {152; CHECK-NEXT: v0.w += vasl(v1.w,r0)153; CHECK-NEXT: jumpr r31154; CHECK-NEXT: }155 %b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0156 %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer157 %v0 = shl <32 x i32> %a1, %b1158 %v1 = add <32 x i32> %a0, %v0159 ret <32 x i32> %v1160}161 162define <32 x i32> @test0024(<32 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {163; CHECK-LABEL: test0024:164; CHECK: // %bb.0:165; CHECK-NEXT: {166; CHECK-NEXT: v0.w += vasr(v1.w,r0)167; CHECK-NEXT: jumpr r31168; CHECK-NEXT: }169 %b0 = insertelement <32 x i32> zeroinitializer, i32 %a2, i32 0170 %b1 = shufflevector <32 x i32> %b0, <32 x i32> undef, <32 x i32> zeroinitializer171 %v0 = ashr <32 x i32> %a1, %b1172 %v1 = add <32 x i32> %a0, %v0173 ret <32 x i32> %v1174}175 176define <128 x i8> @test0030(<128 x i8> %a0, <128 x i8> %a1) #0 {177; CHECK-LABEL: test0030:178; CHECK: // %bb.0:179; CHECK-NEXT: {180; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)181; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)182; CHECK-NEXT: }183; CHECK-NEXT: {184; CHECK-NEXT: v0.h = vasl(v2.h,v30.h)185; CHECK-NEXT: }186; CHECK-NEXT: {187; CHECK-NEXT: v1.h = vasl(v3.h,v31.h)188; CHECK-NEXT: }189; CHECK-NEXT: {190; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)191; CHECK-NEXT: jumpr r31192; CHECK-NEXT: }193 %v0 = shl <128 x i8> %a0, %a1194 ret <128 x i8> %v0195}196 197define <128 x i8> @test0031(<128 x i8> %a0, <128 x i8> %a1) #0 {198; CHECK-LABEL: test0031:199; CHECK: // %bb.0:200; CHECK-NEXT: {201; CHECK-NEXT: v3:2.h = vsxt(v0.b)202; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)203; CHECK-NEXT: }204; CHECK-NEXT: {205; CHECK-NEXT: v0.h = vasr(v2.h,v30.h)206; CHECK-NEXT: }207; CHECK-NEXT: {208; CHECK-NEXT: v1.h = vasr(v3.h,v31.h)209; CHECK-NEXT: }210; CHECK-NEXT: {211; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)212; CHECK-NEXT: jumpr r31213; CHECK-NEXT: }214 %v0 = ashr <128 x i8> %a0, %a1215 ret <128 x i8> %v0216}217 218define <128 x i8> @test0032(<128 x i8> %a0, <128 x i8> %a1) #0 {219; CHECK-LABEL: test0032:220; CHECK: // %bb.0:221; CHECK-NEXT: {222; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)223; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)224; CHECK-NEXT: }225; CHECK-NEXT: {226; CHECK-NEXT: v0.h = vlsr(v2.h,v30.h)227; CHECK-NEXT: }228; CHECK-NEXT: {229; CHECK-NEXT: v1.h = vlsr(v3.h,v31.h)230; CHECK-NEXT: }231; CHECK-NEXT: {232; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)233; CHECK-NEXT: jumpr r31234; CHECK-NEXT: }235 %v0 = lshr <128 x i8> %a0, %a1236 ret <128 x i8> %v0237}238 239define <64 x i16> @test0040(<64 x i16> %a0, <64 x i16> %a1) #0 {240; CHECK-LABEL: test0040:241; CHECK: // %bb.0:242; CHECK-NEXT: {243; CHECK-NEXT: v0.h = vasl(v0.h,v1.h)244; CHECK-NEXT: jumpr r31245; CHECK-NEXT: }246 %v0 = shl <64 x i16> %a0, %a1247 ret <64 x i16> %v0248}249 250define <64 x i16> @test0041(<64 x i16> %a0, <64 x i16> %a1) #0 {251; CHECK-LABEL: test0041:252; CHECK: // %bb.0:253; CHECK-NEXT: {254; CHECK-NEXT: v0.h = vasr(v0.h,v1.h)255; CHECK-NEXT: jumpr r31256; CHECK-NEXT: }257 %v0 = ashr <64 x i16> %a0, %a1258 ret <64 x i16> %v0259}260 261define <64 x i16> @test0042(<64 x i16> %a0, <64 x i16> %a1) #0 {262; CHECK-LABEL: test0042:263; CHECK: // %bb.0:264; CHECK-NEXT: {265; CHECK-NEXT: v0.h = vlsr(v0.h,v1.h)266; CHECK-NEXT: jumpr r31267; CHECK-NEXT: }268 %v0 = lshr <64 x i16> %a0, %a1269 ret <64 x i16> %v0270}271 272define <32 x i32> @test0050(<32 x i32> %a0, <32 x i32> %a1) #0 {273; CHECK-LABEL: test0050:274; CHECK: // %bb.0:275; CHECK-NEXT: {276; CHECK-NEXT: v0.w = vasl(v0.w,v1.w)277; CHECK-NEXT: jumpr r31278; CHECK-NEXT: }279 %v0 = shl <32 x i32> %a0, %a1280 ret <32 x i32> %v0281}282 283define <32 x i32> @test0051(<32 x i32> %a0, <32 x i32> %a1) #0 {284; CHECK-LABEL: test0051:285; CHECK: // %bb.0:286; CHECK-NEXT: {287; CHECK-NEXT: v0.w = vasr(v0.w,v1.w)288; CHECK-NEXT: jumpr r31289; CHECK-NEXT: }290 %v0 = ashr <32 x i32> %a0, %a1291 ret <32 x i32> %v0292}293 294define <32 x i32> @test0052(<32 x i32> %a0, <32 x i32> %a1) #0 {295; CHECK-LABEL: test0052:296; CHECK: // %bb.0:297; CHECK-NEXT: {298; CHECK-NEXT: v0.w = vlsr(v0.w,v1.w)299; CHECK-NEXT: jumpr r31300; CHECK-NEXT: }301 %v0 = lshr <32 x i32> %a0, %a1302 ret <32 x i32> %v0303}304 305attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }306 307