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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4define <64 x i8> @test0000(<64 x i8> %a0, i8 %a1) #0 {5; CHECK-LABEL: test0000:6; CHECK: // %bb.0:7; CHECK-NEXT: {8; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)9; CHECK-NEXT: }10; CHECK-NEXT: {11; CHECK-NEXT: v0.h = vasl(v0.h,r0)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: v1.h = vasl(v1.h,r0)15; CHECK-NEXT: }16; CHECK-NEXT: {17; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)18; CHECK-NEXT: jumpr r3119; CHECK-NEXT: }20 %b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 021 %b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer22 %v0 = shl <64 x i8> %a0, %b123 ret <64 x i8> %v024}25 26define <64 x i8> @test0001(<64 x i8> %a0, i8 %a1) #0 {27; CHECK-LABEL: test0001:28; CHECK: // %bb.0:29; CHECK-NEXT: {30; CHECK-NEXT: v1:0.h = vsxt(v0.b)31; CHECK-NEXT: }32; CHECK-NEXT: {33; CHECK-NEXT: v0.h = vasr(v0.h,r0)34; CHECK-NEXT: }35; CHECK-NEXT: {36; CHECK-NEXT: v1.h = vasr(v1.h,r0)37; CHECK-NEXT: }38; CHECK-NEXT: {39; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)40; CHECK-NEXT: jumpr r3141; CHECK-NEXT: }42 %b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 043 %b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer44 %v0 = ashr <64 x i8> %a0, %b145 ret <64 x i8> %v046}47 48define <64 x i8> @test0002(<64 x i8> %a0, i8 %a1) #0 {49; CHECK-LABEL: test0002:50; CHECK: // %bb.0:51; CHECK-NEXT: {52; CHECK-NEXT: v1:0.uh = vzxt(v0.ub)53; CHECK-NEXT: }54; CHECK-NEXT: {55; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)56; CHECK-NEXT: }57; CHECK-NEXT: {58; CHECK-NEXT: v1.uh = vlsr(v1.uh,r0)59; CHECK-NEXT: }60; CHECK-NEXT: {61; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)62; CHECK-NEXT: jumpr r3163; CHECK-NEXT: }64 %b0 = insertelement <64 x i8> zeroinitializer, i8 %a1, i32 065 %b1 = shufflevector <64 x i8> %b0, <64 x i8> undef, <64 x i32> zeroinitializer66 %v0 = lshr <64 x i8> %a0, %b167 ret <64 x i8> %v068}69 70define <32 x i16> @test0010(<32 x i16> %a0, i16 %a1) #0 {71; CHECK-LABEL: test0010:72; CHECK: // %bb.0:73; CHECK-NEXT: {74; CHECK-NEXT: v0.h = vasl(v0.h,r0)75; CHECK-NEXT: jumpr r3176; CHECK-NEXT: }77 %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 078 %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer79 80 %v0 = shl <32 x i16> %a0, %b181 ret <32 x i16> %v082}83 84define <32 x i16> @test0011(<32 x i16> %a0, i16 %a1) #0 {85; CHECK-LABEL: test0011:86; CHECK: // %bb.0:87; CHECK-NEXT: {88; CHECK-NEXT: v0.h = vasr(v0.h,r0)89; CHECK-NEXT: jumpr r3190; CHECK-NEXT: }91 %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 092 %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer93 %v0 = ashr <32 x i16> %a0, %b194 ret <32 x i16> %v095}96 97define <32 x i16> @test0012(<32 x i16> %a0, i16 %a1) #0 {98; CHECK-LABEL: test0012:99; CHECK: // %bb.0:100; CHECK-NEXT: {101; CHECK-NEXT: v0.uh = vlsr(v0.uh,r0)102; CHECK-NEXT: jumpr r31103; CHECK-NEXT: }104 %b0 = insertelement <32 x i16> zeroinitializer, i16 %a1, i32 0105 %b1 = shufflevector <32 x i16> %b0, <32 x i16> undef, <32 x i32> zeroinitializer106 %v0 = lshr <32 x i16> %a0, %b1107 ret <32 x i16> %v0108}109 110define <16 x i32> @test0020(<16 x i32> %a0, i32 %a1) #0 {111; CHECK-LABEL: test0020:112; CHECK: // %bb.0:113; CHECK-NEXT: {114; CHECK-NEXT: v0.w = vasl(v0.w,r0)115; CHECK-NEXT: jumpr r31116; CHECK-NEXT: }117 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0118 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer119 %v0 = shl <16 x i32> %a0, %b1120 ret <16 x i32> %v0121}122 123define <16 x i32> @test0021(<16 x i32> %a0, i32 %a1) #0 {124; CHECK-LABEL: test0021:125; CHECK: // %bb.0:126; CHECK-NEXT: {127; CHECK-NEXT: v0.w = vasr(v0.w,r0)128; CHECK-NEXT: jumpr r31129; CHECK-NEXT: }130 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0131 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer132 %v0 = ashr <16 x i32> %a0, %b1133 ret <16 x i32> %v0134}135 136define <16 x i32> @test0022(<16 x i32> %a0, i32 %a1) #0 {137; CHECK-LABEL: test0022:138; CHECK: // %bb.0:139; CHECK-NEXT: {140; CHECK-NEXT: v0.uw = vlsr(v0.uw,r0)141; CHECK-NEXT: jumpr r31142; CHECK-NEXT: }143 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a1, i32 0144 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer145 %v0 = lshr <16 x i32> %a0, %b1146 ret <16 x i32> %v0147}148 149define <16 x i32> @test0023(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {150; CHECK-LABEL: test0023:151; CHECK: // %bb.0:152; CHECK-NEXT: {153; CHECK-NEXT: v0.w += vasl(v1.w,r0)154; CHECK-NEXT: jumpr r31155; CHECK-NEXT: }156 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0157 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer158 %v0 = shl <16 x i32> %a1, %b1159 %v1 = add <16 x i32> %a0, %v0160 ret <16 x i32> %v1161}162 163define <16 x i32> @test0024(<16 x i32> %a0, <16 x i32> %a1, i32 %a2) #0 {164; CHECK-LABEL: test0024:165; CHECK: // %bb.0:166; CHECK-NEXT: {167; CHECK-NEXT: v0.w += vasr(v1.w,r0)168; CHECK-NEXT: jumpr r31169; CHECK-NEXT: }170 %b0 = insertelement <16 x i32> zeroinitializer, i32 %a2, i32 0171 %b1 = shufflevector <16 x i32> %b0, <16 x i32> undef, <16 x i32> zeroinitializer172 %v0 = ashr <16 x i32> %a1, %b1173 %v1 = add <16 x i32> %a0, %v0174 ret <16 x i32> %v1175}176 177define <64 x i8> @test0030(<64 x i8> %a0, <64 x i8> %a1) #0 {178; CHECK-LABEL: test0030:179; CHECK: // %bb.0:180; CHECK-NEXT: {181; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)182; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)183; CHECK-NEXT: }184; CHECK-NEXT: {185; CHECK-NEXT: v0.h = vasl(v2.h,v30.h)186; CHECK-NEXT: }187; CHECK-NEXT: {188; CHECK-NEXT: v1.h = vasl(v3.h,v31.h)189; CHECK-NEXT: }190; CHECK-NEXT: {191; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)192; CHECK-NEXT: jumpr r31193; CHECK-NEXT: }194 %v0 = shl <64 x i8> %a0, %a1195 ret <64 x i8> %v0196}197 198define <64 x i8> @test0031(<64 x i8> %a0, <64 x i8> %a1) #0 {199; CHECK-LABEL: test0031:200; CHECK: // %bb.0:201; CHECK-NEXT: {202; CHECK-NEXT: v3:2.h = vsxt(v0.b)203; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)204; CHECK-NEXT: }205; CHECK-NEXT: {206; CHECK-NEXT: v0.h = vasr(v2.h,v30.h)207; CHECK-NEXT: }208; CHECK-NEXT: {209; CHECK-NEXT: v1.h = vasr(v3.h,v31.h)210; CHECK-NEXT: }211; CHECK-NEXT: {212; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)213; CHECK-NEXT: jumpr r31214; CHECK-NEXT: }215 %v0 = ashr <64 x i8> %a0, %a1216 ret <64 x i8> %v0217}218 219define <64 x i8> @test0032(<64 x i8> %a0, <64 x i8> %a1) #0 {220; CHECK-LABEL: test0032:221; CHECK: // %bb.0:222; CHECK-NEXT: {223; CHECK-NEXT: v3:2.uh = vzxt(v0.ub)224; CHECK-NEXT: v31:30.uh = vzxt(v1.ub)225; CHECK-NEXT: }226; CHECK-NEXT: {227; CHECK-NEXT: v0.h = vlsr(v2.h,v30.h)228; CHECK-NEXT: }229; CHECK-NEXT: {230; CHECK-NEXT: v1.h = vlsr(v3.h,v31.h)231; CHECK-NEXT: }232; CHECK-NEXT: {233; CHECK-NEXT: v0.b = vshuffe(v1.b,v0.b)234; CHECK-NEXT: jumpr r31235; CHECK-NEXT: }236 %v0 = lshr <64 x i8> %a0, %a1237 ret <64 x i8> %v0238}239 240define <32 x i16> @test0040(<32 x i16> %a0, <32 x i16> %a1) #0 {241; CHECK-LABEL: test0040:242; CHECK: // %bb.0:243; CHECK-NEXT: {244; CHECK-NEXT: v0.h = vasl(v0.h,v1.h)245; CHECK-NEXT: jumpr r31246; CHECK-NEXT: }247 %v0 = shl <32 x i16> %a0, %a1248 ret <32 x i16> %v0249}250 251define <32 x i16> @test0041(<32 x i16> %a0, <32 x i16> %a1) #0 {252; CHECK-LABEL: test0041:253; CHECK: // %bb.0:254; CHECK-NEXT: {255; CHECK-NEXT: v0.h = vasr(v0.h,v1.h)256; CHECK-NEXT: jumpr r31257; CHECK-NEXT: }258 %v0 = ashr <32 x i16> %a0, %a1259 ret <32 x i16> %v0260}261 262define <32 x i16> @test0042(<32 x i16> %a0, <32 x i16> %a1) #0 {263; CHECK-LABEL: test0042:264; CHECK: // %bb.0:265; CHECK-NEXT: {266; CHECK-NEXT: v0.h = vlsr(v0.h,v1.h)267; CHECK-NEXT: jumpr r31268; CHECK-NEXT: }269 %v0 = lshr <32 x i16> %a0, %a1270 ret <32 x i16> %v0271}272 273define <16 x i32> @test0050(<16 x i32> %a0, <16 x i32> %a1) #0 {274; CHECK-LABEL: test0050:275; CHECK: // %bb.0:276; CHECK-NEXT: {277; CHECK-NEXT: v0.w = vasl(v0.w,v1.w)278; CHECK-NEXT: jumpr r31279; CHECK-NEXT: }280 %v0 = shl <16 x i32> %a0, %a1281 ret <16 x i32> %v0282}283 284define <16 x i32> @test0051(<16 x i32> %a0, <16 x i32> %a1) #0 {285; CHECK-LABEL: test0051:286; CHECK: // %bb.0:287; CHECK-NEXT: {288; CHECK-NEXT: v0.w = vasr(v0.w,v1.w)289; CHECK-NEXT: jumpr r31290; CHECK-NEXT: }291 %v0 = ashr <16 x i32> %a0, %a1292 ret <16 x i32> %v0293}294 295define <16 x i32> @test0052(<16 x i32> %a0, <16 x i32> %a1) #0 {296; CHECK-LABEL: test0052:297; CHECK: // %bb.0:298; CHECK-NEXT: {299; CHECK-NEXT: v0.w = vlsr(v0.w,v1.w)300; CHECK-NEXT: jumpr r31301; CHECK-NEXT: }302 %v0 = lshr <16 x i32> %a0, %a1303 ret <16 x i32> %v0304}305 306attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }307 308