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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4; Function Attrs: nounwind5define <32 x i32> @f0(ptr %a0, i32 %a1) #0 {6; CHECK-LABEL: f0:7; CHECK: // %bb.0: // %b08; CHECK-NEXT: {9; CHECK-NEXT: r0 = add(r1,r0)10; CHECK-NEXT: }11; CHECK-NEXT: {12; CHECK-NEXT: r7 = #813; CHECK-NEXT: }14; CHECK-NEXT: {15; CHECK-NEXT: r4 = ##.LCPI0_016; CHECK-NEXT: }17; CHECK-NEXT: {18; CHECK-NEXT: r2 = #-119; CHECK-NEXT: }20; CHECK-NEXT: {21; CHECK-NEXT: v0 = vmem(r0+#1)22; CHECK-NEXT: }23; CHECK-NEXT: {24; CHECK-NEXT: v1 = vmem(r0+#2)25; CHECK-NEXT: }26; CHECK-NEXT: {27; CHECK-NEXT: r0 = add(r0,#128)28; CHECK-NEXT: }29; CHECK-NEXT: {30; CHECK-NEXT: v1 = valign(v1,v0,r7)31; CHECK-NEXT: }32; CHECK-NEXT: {33; CHECK-NEXT: v2 = vmem(r4+#0)34; CHECK-NEXT: }35; CHECK-NEXT: {36; CHECK-NEXT: q0 = vand(v2,r2)37; CHECK-NEXT: }38; CHECK-NEXT: {39; CHECK-NEXT: v0.w = vadd(v0.w,v1.w)40; CHECK-NEXT: }41; CHECK-NEXT: {42; CHECK-NEXT: if (q0) vmem(r0+#0) = v043; CHECK-NEXT: }44; CHECK-NEXT: {45; CHECK-NEXT: jumpr r3146; CHECK-NEXT: }47b0:48 %v0 = add i32 %a1, 12849 %v1 = getelementptr i8, ptr %a0, i32 %v050 %v3 = tail call <32 x i32> @llvm.masked.load.v32i32.p0(ptr %v1, i32 128, <32 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i32> undef)51 %v4 = add i32 %a1, 13652 %v5 = getelementptr i8, ptr %a0, i32 %v453 %v7 = tail call <32 x i32> @llvm.masked.load.v32i32.p0(ptr %v5, i32 8, <32 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <32 x i32> undef)54 %v8 = add <32 x i32> %v3, %v755 tail call void @llvm.masked.store.v32i32.p0(<32 x i32> %v8, ptr %v1, i32 128, <32 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>)56 ret <32 x i32> %v857}58 59; Function Attrs: argmemonly nounwind readonly willreturn60declare <32 x i32> @llvm.masked.load.v32i32.p0(ptr, i32 immarg, <32 x i1>, <32 x i32>) #161 62; Function Attrs: argmemonly nounwind willreturn63declare void @llvm.masked.store.v32i32.p0(<32 x i32>, ptr, i32 immarg, <32 x i1>) #264 65attributes #0 = { nounwind "target-cpu"="hexagonv66" "target-features"="+hvxv66,+hvx-length128b,-packets" }66attributes #1 = { argmemonly nounwind readonly willreturn }67attributes #2 = { argmemonly nounwind willreturn }68