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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon < %s | FileCheck %s3 4; In this testcase, when loads were moved close to users, they were actualy5; moved right before the consuming stores. This was after the store group6; was moved, so the loads and stores ended up being interleaved. This violated7; the assumption in store realigning that all loads were available before the8; first store, causing some code depending on the loads being inserted before9; the load used.10; Just make sure that this compiles ok.11 12; Function Attrs: nounwind13define void @f0(ptr noalias nocapture readonly %a0, ptr noalias nocapture %a1, i32 %a2) #0 {14; CHECK-LABEL: f0:15; CHECK: // %bb.0: // %b016; CHECK-NEXT: {17; CHECK-NEXT: p0 = cmp.eq(r2,#0)18; CHECK-NEXT: if (p0.new) jumpr:nt r3119; CHECK-NEXT: }20; CHECK-NEXT: .p2align 421; CHECK-NEXT: .LBB0_1: // %b222; CHECK-NEXT: // =>This Inner Loop Header: Depth=123; CHECK-NEXT: {24; CHECK-NEXT: v0.cur = vmem(r0+#0)25; CHECK-NEXT: vmem(r1+#0) = v026; CHECK-NEXT: }27; CHECK-NEXT: {28; CHECK-NEXT: v29.cur = vmem(r0+#1)29; CHECK-NEXT: vmem(r1+#1) = v2930; CHECK-NEXT: }31; CHECK-NEXT: {32; CHECK-NEXT: v30.cur = vmem(r0+#2)33; CHECK-NEXT: vmem(r1+#2) = v3034; CHECK-NEXT: }35; CHECK-NEXT: {36; CHECK-NEXT: r0 = add(r0,#256)37; CHECK-NEXT: r1 = add(r1,#256)38; CHECK-NEXT: v31.cur = vmem(r0+#3)39; CHECK-NEXT: vmem(r1+#3) = v3140; CHECK-NEXT: }41; CHECK-NEXT: {42; CHECK-NEXT: jump .LBB0_143; CHECK-NEXT: }44b0:45 %v0 = icmp eq i32 %a2, 046 br i1 %v0, label %b3, label %b147 48b1: ; preds = %b049 br label %b250 51b2: ; preds = %b2, %b152 %v3 = phi ptr [ %v16, %b2 ], [ %a1, %b1 ]53 %v4 = phi ptr [ %v11, %b2 ], [ %a0, %b1 ]54 %v5 = getelementptr inbounds <16 x i32>, ptr %v4, i32 155 %v6 = load <16 x i32>, ptr %v4, align 6456 %v7 = getelementptr inbounds <16 x i32>, ptr %v4, i32 257 %v8 = load <16 x i32>, ptr %v5, align 6458 %v9 = getelementptr inbounds <16 x i32>, ptr %v4, i32 359 %v10 = load <16 x i32>, ptr %v7, align 6460 %v11 = getelementptr inbounds <16 x i32>, ptr %v4, i32 461 %v12 = load <16 x i32>, ptr %v9, align 6462 %v13 = getelementptr inbounds <16 x i32>, ptr %v3, i32 163 store <16 x i32> %v6, ptr %v3, align 6464 %v14 = getelementptr inbounds <16 x i32>, ptr %v3, i32 265 store <16 x i32> %v8, ptr %v13, align 6466 %v15 = getelementptr inbounds <16 x i32>, ptr %v3, i32 367 store <16 x i32> %v10, ptr %v14, align 6468 %v16 = getelementptr inbounds <16 x i32>, ptr %v3, i32 469 store <16 x i32> %v12, ptr %v15, align 6470 br label %b271 72b3: ; preds = %b073 ret void74}75 76attributes #0 = { nounwind "target-features"="+hvxv65,+hvx-length64b" }77