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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -mtriple=hexagon -S -hexagon-vc -instcombine -hvc-va-full-stores < %s | FileCheck %s3 4; Check that Hexagon Vector Combine propagates (TBAA) metadata to the5; generated output. (Use instcombine to clean the output up a bit.)6 7target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"8target triple = "hexagon"9 10; Two unaligned loads, both with the same TBAA tag.11;12define <64 x i16> @f0(ptr %a0, i32 %a1) #0 {13; CHECK-LABEL: @f0(14; CHECK-NEXT: b0:15; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i16, ptr [[A0:%.*]], i32 [[A1:%.*]]16; CHECK-NEXT: [[V1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12817; CHECK-NEXT: [[PTI:%.*]] = ptrtoint ptr [[V1]] to i3218; CHECK-NEXT: [[AND:%.*]] = and i32 [[PTI]], -12819; CHECK-NEXT: [[ITP:%.*]] = inttoptr i32 [[AND]] to ptr20; CHECK-NEXT: [[PTI1:%.*]] = ptrtoint ptr [[V1]] to i3221; CHECK-NEXT: [[ALD14:%.*]] = load <32 x i32>, ptr [[ITP]], align 128, !tbaa [[TBAA0:![0-9]+]]22; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ITP]], i32 12823; CHECK-NEXT: [[ALD2:%.*]] = load <128 x i8>, ptr [[GEP]], align 128, !tbaa [[TBAA0]]24; CHECK-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr [[ITP]], i32 25625; CHECK-NEXT: [[AND4:%.*]] = and i32 [[PTI1]], 12726; CHECK-NEXT: [[ISZ:%.*]] = icmp ne i32 [[AND4]], 027; CHECK-NEXT: [[CUP:%.*]] = call <32 x i32> @llvm.hexagon.V6.vL32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP3]], i32 0), !tbaa [[TBAA0]]28; CHECK-NEXT: [[CST5:%.*]] = bitcast <128 x i8> [[ALD2]] to <32 x i32>29; CHECK-NEXT: [[CUP7:%.*]] = call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> [[CST5]], <32 x i32> [[ALD14]], i32 [[PTI1]])30; CHECK-NEXT: [[CST12:%.*]] = bitcast <32 x i32> [[CUP7]] to <64 x i16>31; CHECK-NEXT: [[CST9:%.*]] = bitcast <128 x i8> [[ALD2]] to <32 x i32>32; CHECK-NEXT: [[CUP10:%.*]] = call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> [[CUP]], <32 x i32> [[CST9]], i32 [[PTI1]])33; CHECK-NEXT: [[CST13:%.*]] = bitcast <32 x i32> [[CUP10]] to <64 x i16>34; CHECK-NEXT: [[V8:%.*]] = add <64 x i16> [[CST12]], [[CST13]]35; CHECK-NEXT: ret <64 x i16> [[V8]]36;37b0:38 %v0 = add i32 %a1, 6439 %v1 = getelementptr i16, ptr %a0, i32 %v040 %v3 = load <64 x i16>, ptr %v1, align 2, !tbaa !041 %v4 = add i32 %a1, 12842 %v5 = getelementptr i16, ptr %a0, i32 %v443 %v7 = load <64 x i16>, ptr %v5, align 2, !tbaa !044 %v8 = add <64 x i16> %v3, %v745 ret <64 x i16> %v846}47 48; Two unaligned loads, only one with a TBAA tag.49;50define <64 x i16> @f1(ptr %a0, i32 %a1) #0 {51; CHECK-LABEL: @f1(52; CHECK-NEXT: b0:53; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i16, ptr [[A0:%.*]], i32 [[A1:%.*]]54; CHECK-NEXT: [[V1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12855; CHECK-NEXT: [[PTI:%.*]] = ptrtoint ptr [[V1]] to i3256; CHECK-NEXT: [[AND:%.*]] = and i32 [[PTI]], -12857; CHECK-NEXT: [[ITP:%.*]] = inttoptr i32 [[AND]] to ptr58; CHECK-NEXT: [[PTI1:%.*]] = ptrtoint ptr [[V1]] to i3259; CHECK-NEXT: [[ALD14:%.*]] = load <32 x i32>, ptr [[ITP]], align 128, !tbaa [[TBAA0]]60; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ITP]], i32 12861; CHECK-NEXT: [[ALD2:%.*]] = load <128 x i8>, ptr [[GEP]], align 12862; CHECK-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr [[ITP]], i32 25663; CHECK-NEXT: [[AND4:%.*]] = and i32 [[PTI1]], 12764; CHECK-NEXT: [[ISZ:%.*]] = icmp ne i32 [[AND4]], 065; CHECK-NEXT: [[CUP:%.*]] = call <32 x i32> @llvm.hexagon.V6.vL32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP3]], i32 0)66; CHECK-NEXT: [[CST5:%.*]] = bitcast <128 x i8> [[ALD2]] to <32 x i32>67; CHECK-NEXT: [[CUP7:%.*]] = call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> [[CST5]], <32 x i32> [[ALD14]], i32 [[PTI1]])68; CHECK-NEXT: [[CST12:%.*]] = bitcast <32 x i32> [[CUP7]] to <64 x i16>69; CHECK-NEXT: [[CST9:%.*]] = bitcast <128 x i8> [[ALD2]] to <32 x i32>70; CHECK-NEXT: [[CUP10:%.*]] = call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> [[CUP]], <32 x i32> [[CST9]], i32 [[PTI1]])71; CHECK-NEXT: [[CST13:%.*]] = bitcast <32 x i32> [[CUP10]] to <64 x i16>72; CHECK-NEXT: [[V8:%.*]] = add <64 x i16> [[CST12]], [[CST13]]73; CHECK-NEXT: ret <64 x i16> [[V8]]74;75b0:76 %v0 = add i32 %a1, 6477 %v1 = getelementptr i16, ptr %a0, i32 %v078 %v3 = load <64 x i16>, ptr %v1, align 2, !tbaa !079 %v4 = add i32 %a1, 12880 %v5 = getelementptr i16, ptr %a0, i32 %v481 %v7 = load <64 x i16>, ptr %v5, align 282 %v8 = add <64 x i16> %v3, %v783 ret <64 x i16> %v884}85 86; Two unaligned loads, with different TBAA tags.87;88define <64 x i16> @f2(ptr %a0, i32 %a1) #0 {89; CHECK-LABEL: @f2(90; CHECK-NEXT: b0:91; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i16, ptr [[A0:%.*]], i32 [[A1:%.*]]92; CHECK-NEXT: [[V1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 12893; CHECK-NEXT: [[PTI:%.*]] = ptrtoint ptr [[V1]] to i3294; CHECK-NEXT: [[AND:%.*]] = and i32 [[PTI]], -12895; CHECK-NEXT: [[ITP:%.*]] = inttoptr i32 [[AND]] to ptr96; CHECK-NEXT: [[PTI1:%.*]] = ptrtoint ptr [[V1]] to i3297; CHECK-NEXT: [[ALD14:%.*]] = load <32 x i32>, ptr [[ITP]], align 128, !tbaa [[TBAA0]]98; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ITP]], i32 12899; CHECK-NEXT: [[ALD2:%.*]] = load <128 x i8>, ptr [[GEP]], align 128100; CHECK-NEXT: [[GEP3:%.*]] = getelementptr i8, ptr [[ITP]], i32 256101; CHECK-NEXT: [[AND4:%.*]] = and i32 [[PTI1]], 127102; CHECK-NEXT: [[ISZ:%.*]] = icmp ne i32 [[AND4]], 0103; CHECK-NEXT: [[CUP:%.*]] = call <32 x i32> @llvm.hexagon.V6.vL32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP3]], i32 0), !tbaa [[TBAA3:![0-9]+]]104; CHECK-NEXT: [[CST5:%.*]] = bitcast <128 x i8> [[ALD2]] to <32 x i32>105; CHECK-NEXT: [[CUP7:%.*]] = call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> [[CST5]], <32 x i32> [[ALD14]], i32 [[PTI1]])106; CHECK-NEXT: [[CST12:%.*]] = bitcast <32 x i32> [[CUP7]] to <64 x i16>107; CHECK-NEXT: [[CST9:%.*]] = bitcast <128 x i8> [[ALD2]] to <32 x i32>108; CHECK-NEXT: [[CUP10:%.*]] = call <32 x i32> @llvm.hexagon.V6.valignb.128B(<32 x i32> [[CUP]], <32 x i32> [[CST9]], i32 [[PTI1]])109; CHECK-NEXT: [[CST13:%.*]] = bitcast <32 x i32> [[CUP10]] to <64 x i16>110; CHECK-NEXT: [[V8:%.*]] = add <64 x i16> [[CST12]], [[CST13]]111; CHECK-NEXT: ret <64 x i16> [[V8]]112;113b0:114 %v0 = add i32 %a1, 64115 %v1 = getelementptr i16, ptr %a0, i32 %v0116 %v3 = load <64 x i16>, ptr %v1, align 2, !tbaa !0117 %v4 = add i32 %a1, 128118 %v5 = getelementptr i16, ptr %a0, i32 %v4119 %v7 = load <64 x i16>, ptr %v5, align 2, !tbaa !3120 %v8 = add <64 x i16> %v3, %v7121 ret <64 x i16> %v8122}123 124; Two unaligned stores, both with the same TBAA tag.125;126define void @f3(ptr %a0, i32 %a1, <64 x i16> %a2, <64 x i16> %a3) #0 {127; CHECK-LABEL: @f3(128; CHECK-NEXT: b0:129; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i16, ptr [[A0:%.*]], i32 [[A1:%.*]]130; CHECK-NEXT: [[V1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 128131; CHECK-NEXT: [[PTI:%.*]] = ptrtoint ptr [[V1]] to i32132; CHECK-NEXT: [[AND:%.*]] = and i32 [[PTI]], -128133; CHECK-NEXT: [[ITP:%.*]] = inttoptr i32 [[AND]] to ptr134; CHECK-NEXT: [[PTI1:%.*]] = ptrtoint ptr [[V1]] to i32135; CHECK-NEXT: [[CST3:%.*]] = bitcast <64 x i16> [[A2:%.*]] to <32 x i32>136; CHECK-NEXT: [[CUP:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> [[CST3]], <32 x i32> undef, i32 [[PTI1]])137; CHECK-NEXT: [[CST4:%.*]] = bitcast <32 x i32> [[CUP]] to <128 x i8>138; CHECK-NEXT: [[CUP5:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> splat (i32 -1), <32 x i32> zeroinitializer, i32 [[PTI1]])139; CHECK-NEXT: [[CST6:%.*]] = bitcast <32 x i32> [[CUP5]] to <128 x i8>140; CHECK-NEXT: [[CST7:%.*]] = bitcast <64 x i16> [[A3:%.*]] to <32 x i32>141; CHECK-NEXT: [[CST8:%.*]] = bitcast <64 x i16> [[A2]] to <32 x i32>142; CHECK-NEXT: [[CUP9:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> [[CST7]], <32 x i32> [[CST8]], i32 [[PTI1]])143; CHECK-NEXT: [[CST10:%.*]] = bitcast <32 x i32> [[CUP9]] to <128 x i8>144; CHECK-NEXT: [[CUP11:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> splat (i32 -1), <32 x i32> splat (i32 -1), i32 [[PTI1]])145; CHECK-NEXT: [[CST12:%.*]] = bitcast <32 x i32> [[CUP11]] to <128 x i8>146; CHECK-NEXT: [[CST13:%.*]] = bitcast <64 x i16> [[A3]] to <32 x i32>147; CHECK-NEXT: [[CUP14:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> undef, <32 x i32> [[CST13]], i32 [[PTI1]])148; CHECK-NEXT: [[CST15:%.*]] = bitcast <32 x i32> [[CUP14]] to <128 x i8>149; CHECK-NEXT: [[CUP16:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> zeroinitializer, <32 x i32> splat (i32 -1), i32 [[PTI1]])150; CHECK-NEXT: [[CST17:%.*]] = bitcast <32 x i32> [[CUP16]] to <128 x i8>151; CHECK-NEXT: [[TRN:%.*]] = trunc <128 x i8> [[CST6]] to <128 x i1>152; CHECK-NEXT: call void @llvm.masked.store.v128i8.p0(<128 x i8> [[CST4]], ptr align 128 [[ITP]], <128 x i1> [[TRN]]), !tbaa [[TBAA5:![0-9]+]]153; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ITP]], i32 128154; CHECK-NEXT: [[TRN18:%.*]] = trunc <128 x i8> [[CST12]] to <128 x i1>155; CHECK-NEXT: call void @llvm.masked.store.v128i8.p0(<128 x i8> [[CST10]], ptr align 128 [[GEP]], <128 x i1> [[TRN18]]), !tbaa [[TBAA5]]156; CHECK-NEXT: [[GEP19:%.*]] = getelementptr i8, ptr [[ITP]], i32 256157; CHECK-NEXT: [[AND20:%.*]] = and i32 [[PTI1]], 127158; CHECK-NEXT: [[ISZ:%.*]] = icmp ne i32 [[AND20]], 0159; CHECK-NEXT: [[TRN21:%.*]] = trunc <128 x i8> [[CST17]] to <128 x i1>160; CHECK-NEXT: [[CUP22:%.*]] = call <32 x i32> @llvm.hexagon.V6.vL32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP19]], i32 0), !tbaa [[TBAA5]]161; CHECK-NEXT: [[CST23:%.*]] = bitcast <32 x i32> [[CUP22]] to <128 x i8>162; CHECK-NEXT: [[TMP1:%.*]] = select <128 x i1> [[TRN21]], <128 x i8> [[CST15]], <128 x i8> [[CST23]]163; CHECK-NEXT: [[CST24:%.*]] = bitcast <128 x i8> [[TMP1]] to <32 x i32>164; CHECK-NEXT: call void @llvm.hexagon.V6.vS32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP19]], i32 0, <32 x i32> [[CST24]]), !tbaa [[TBAA5]]165; CHECK-NEXT: ret void166;167b0:168 %v0 = add i32 %a1, 64169 %v1 = getelementptr i16, ptr %a0, i32 %v0170 store <64 x i16> %a2, ptr %v1, align 2, !tbaa !5171 %v3 = add i32 %a1, 128172 %v4 = getelementptr i16, ptr %a0, i32 %v3173 store <64 x i16> %a3, ptr %v4, align 2, !tbaa !5174 ret void175}176 177; Two unaligned stores, only one with a TBAA tag.178;179define void @f4(ptr %a0, i32 %a1, <64 x i16> %a2, <64 x i16> %a3) #0 {180; CHECK-LABEL: @f4(181; CHECK-NEXT: b0:182; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i16, ptr [[A0:%.*]], i32 [[A1:%.*]]183; CHECK-NEXT: [[V1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 128184; CHECK-NEXT: [[PTI:%.*]] = ptrtoint ptr [[V1]] to i32185; CHECK-NEXT: [[AND:%.*]] = and i32 [[PTI]], -128186; CHECK-NEXT: [[ITP:%.*]] = inttoptr i32 [[AND]] to ptr187; CHECK-NEXT: [[PTI1:%.*]] = ptrtoint ptr [[V1]] to i32188; CHECK-NEXT: [[CST3:%.*]] = bitcast <64 x i16> [[A2:%.*]] to <32 x i32>189; CHECK-NEXT: [[CUP:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> [[CST3]], <32 x i32> undef, i32 [[PTI1]])190; CHECK-NEXT: [[CST4:%.*]] = bitcast <32 x i32> [[CUP]] to <128 x i8>191; CHECK-NEXT: [[CUP5:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> splat (i32 -1), <32 x i32> zeroinitializer, i32 [[PTI1]])192; CHECK-NEXT: [[CST6:%.*]] = bitcast <32 x i32> [[CUP5]] to <128 x i8>193; CHECK-NEXT: [[CST7:%.*]] = bitcast <64 x i16> [[A3:%.*]] to <32 x i32>194; CHECK-NEXT: [[CST8:%.*]] = bitcast <64 x i16> [[A2]] to <32 x i32>195; CHECK-NEXT: [[CUP9:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> [[CST7]], <32 x i32> [[CST8]], i32 [[PTI1]])196; CHECK-NEXT: [[CST10:%.*]] = bitcast <32 x i32> [[CUP9]] to <128 x i8>197; CHECK-NEXT: [[CUP11:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> splat (i32 -1), <32 x i32> splat (i32 -1), i32 [[PTI1]])198; CHECK-NEXT: [[CST12:%.*]] = bitcast <32 x i32> [[CUP11]] to <128 x i8>199; CHECK-NEXT: [[CST13:%.*]] = bitcast <64 x i16> [[A3]] to <32 x i32>200; CHECK-NEXT: [[CUP14:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> undef, <32 x i32> [[CST13]], i32 [[PTI1]])201; CHECK-NEXT: [[CST15:%.*]] = bitcast <32 x i32> [[CUP14]] to <128 x i8>202; CHECK-NEXT: [[CUP16:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> zeroinitializer, <32 x i32> splat (i32 -1), i32 [[PTI1]])203; CHECK-NEXT: [[CST17:%.*]] = bitcast <32 x i32> [[CUP16]] to <128 x i8>204; CHECK-NEXT: [[TRN:%.*]] = trunc <128 x i8> [[CST6]] to <128 x i1>205; CHECK-NEXT: call void @llvm.masked.store.v128i8.p0(<128 x i8> [[CST4]], ptr align 128 [[ITP]], <128 x i1> [[TRN]])206; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ITP]], i32 128207; CHECK-NEXT: [[TRN18:%.*]] = trunc <128 x i8> [[CST12]] to <128 x i1>208; CHECK-NEXT: call void @llvm.masked.store.v128i8.p0(<128 x i8> [[CST10]], ptr align 128 [[GEP]], <128 x i1> [[TRN18]])209; CHECK-NEXT: [[GEP19:%.*]] = getelementptr i8, ptr [[ITP]], i32 256210; CHECK-NEXT: [[AND20:%.*]] = and i32 [[PTI1]], 127211; CHECK-NEXT: [[ISZ:%.*]] = icmp ne i32 [[AND20]], 0212; CHECK-NEXT: [[TRN21:%.*]] = trunc <128 x i8> [[CST17]] to <128 x i1>213; CHECK-NEXT: [[CUP22:%.*]] = call <32 x i32> @llvm.hexagon.V6.vL32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP19]], i32 0), !tbaa [[TBAA5]]214; CHECK-NEXT: [[CST23:%.*]] = bitcast <32 x i32> [[CUP22]] to <128 x i8>215; CHECK-NEXT: [[TMP1:%.*]] = select <128 x i1> [[TRN21]], <128 x i8> [[CST15]], <128 x i8> [[CST23]]216; CHECK-NEXT: [[CST24:%.*]] = bitcast <128 x i8> [[TMP1]] to <32 x i32>217; CHECK-NEXT: call void @llvm.hexagon.V6.vS32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP19]], i32 0, <32 x i32> [[CST24]]), !tbaa [[TBAA5]]218; CHECK-NEXT: ret void219;220b0:221 %v0 = add i32 %a1, 64222 %v1 = getelementptr i16, ptr %a0, i32 %v0223 store <64 x i16> %a2, ptr %v1, align 2224 %v3 = add i32 %a1, 128225 %v4 = getelementptr i16, ptr %a0, i32 %v3226 store <64 x i16> %a3, ptr %v4, align 2, !tbaa !5227 ret void228}229 230; Two unaligned store, with different TBAA tags.231;232define void @f5(ptr %a0, i32 %a1, <64 x i16> %a2, <64 x i16> %a3) #0 {233; CHECK-LABEL: @f5(234; CHECK-NEXT: b0:235; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i16, ptr [[A0:%.*]], i32 [[A1:%.*]]236; CHECK-NEXT: [[V1:%.*]] = getelementptr i8, ptr [[TMP0]], i32 128237; CHECK-NEXT: [[PTI:%.*]] = ptrtoint ptr [[V1]] to i32238; CHECK-NEXT: [[AND:%.*]] = and i32 [[PTI]], -128239; CHECK-NEXT: [[ITP:%.*]] = inttoptr i32 [[AND]] to ptr240; CHECK-NEXT: [[PTI1:%.*]] = ptrtoint ptr [[V1]] to i32241; CHECK-NEXT: [[CST3:%.*]] = bitcast <64 x i16> [[A2:%.*]] to <32 x i32>242; CHECK-NEXT: [[CUP:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> [[CST3]], <32 x i32> undef, i32 [[PTI1]])243; CHECK-NEXT: [[CST4:%.*]] = bitcast <32 x i32> [[CUP]] to <128 x i8>244; CHECK-NEXT: [[CUP5:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> splat (i32 -1), <32 x i32> zeroinitializer, i32 [[PTI1]])245; CHECK-NEXT: [[CST6:%.*]] = bitcast <32 x i32> [[CUP5]] to <128 x i8>246; CHECK-NEXT: [[CST7:%.*]] = bitcast <64 x i16> [[A3:%.*]] to <32 x i32>247; CHECK-NEXT: [[CST8:%.*]] = bitcast <64 x i16> [[A2]] to <32 x i32>248; CHECK-NEXT: [[CUP9:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> [[CST7]], <32 x i32> [[CST8]], i32 [[PTI1]])249; CHECK-NEXT: [[CST10:%.*]] = bitcast <32 x i32> [[CUP9]] to <128 x i8>250; CHECK-NEXT: [[CUP11:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> splat (i32 -1), <32 x i32> splat (i32 -1), i32 [[PTI1]])251; CHECK-NEXT: [[CST12:%.*]] = bitcast <32 x i32> [[CUP11]] to <128 x i8>252; CHECK-NEXT: [[CST13:%.*]] = bitcast <64 x i16> [[A3]] to <32 x i32>253; CHECK-NEXT: [[CUP14:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> undef, <32 x i32> [[CST13]], i32 [[PTI1]])254; CHECK-NEXT: [[CST15:%.*]] = bitcast <32 x i32> [[CUP14]] to <128 x i8>255; CHECK-NEXT: [[CUP16:%.*]] = call <32 x i32> @llvm.hexagon.V6.vlalignb.128B(<32 x i32> zeroinitializer, <32 x i32> splat (i32 -1), i32 [[PTI1]])256; CHECK-NEXT: [[CST17:%.*]] = bitcast <32 x i32> [[CUP16]] to <128 x i8>257; CHECK-NEXT: [[TRN:%.*]] = trunc <128 x i8> [[CST6]] to <128 x i1>258; CHECK-NEXT: call void @llvm.masked.store.v128i8.p0(<128 x i8> [[CST4]], ptr align 128 [[ITP]], <128 x i1> [[TRN]]), !tbaa [[TBAA5]]259; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[ITP]], i32 128260; CHECK-NEXT: [[TRN18:%.*]] = trunc <128 x i8> [[CST12]] to <128 x i1>261; CHECK-NEXT: call void @llvm.masked.store.v128i8.p0(<128 x i8> [[CST10]], ptr align 128 [[GEP]], <128 x i1> [[TRN18]])262; CHECK-NEXT: [[GEP19:%.*]] = getelementptr i8, ptr [[ITP]], i32 256263; CHECK-NEXT: [[AND20:%.*]] = and i32 [[PTI1]], 127264; CHECK-NEXT: [[ISZ:%.*]] = icmp ne i32 [[AND20]], 0265; CHECK-NEXT: [[TRN21:%.*]] = trunc <128 x i8> [[CST17]] to <128 x i1>266; CHECK-NEXT: [[CUP22:%.*]] = call <32 x i32> @llvm.hexagon.V6.vL32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP19]], i32 0), !tbaa [[TBAA7:![0-9]+]]267; CHECK-NEXT: [[CST23:%.*]] = bitcast <32 x i32> [[CUP22]] to <128 x i8>268; CHECK-NEXT: [[TMP1:%.*]] = select <128 x i1> [[TRN21]], <128 x i8> [[CST15]], <128 x i8> [[CST23]]269; CHECK-NEXT: [[CST24:%.*]] = bitcast <128 x i8> [[TMP1]] to <32 x i32>270; CHECK-NEXT: call void @llvm.hexagon.V6.vS32b.pred.ai.128B(i1 [[ISZ]], ptr [[GEP19]], i32 0, <32 x i32> [[CST24]]), !tbaa [[TBAA7]]271; CHECK-NEXT: ret void272;273b0:274 %v0 = add i32 %a1, 64275 %v1 = getelementptr i16, ptr %a0, i32 %v0276 store <64 x i16> %a2, ptr %v1, align 2, !tbaa !5277 %v3 = add i32 %a1, 128278 %v4 = getelementptr i16, ptr %a0, i32 %v3279 store <64 x i16> %a3, ptr %v4, align 2, !tbaa !7280 ret void281}282 283attributes #0 = { nounwind "target-cpu"="hexagonv68" "target-features"="+hvxv68,+hvx-length128b" }284 285!0 = !{!1, !1, i64 0}286!1 = !{!"load type 1", !2}287!2 = !{!"Simple C/C++ TBAA"}288!3 = !{!4, !4, i64 0}289!4 = !{!"load type 2", !2}290!5 = !{!6, !6, i64 0}291!6 = !{!"store type 1", !2}292!7 = !{!8, !8, i64 0}293!8 = !{!"store type 2", !2}294