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1; RUN: llc -mtriple=hexagon -hexagon-hvx-widen=32 < %s | FileCheck %s2 3; If the "rx = #N, vsetq(rx)" get reordered with the rest, update the test.4 5; v32i16 -> v32i86; CHECK-LABEL: f0:7; CHECK: r[[R0:[0-9]+]] = #328; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)9; CHECK: v[[V1:[0-9]+]].b = vpacke({{.*}},v[[V0]].h)10; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])11; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]12define void @f0(ptr %a0, ptr %a1) #0 {13 %v0 = load <32 x i16>, ptr %a0, align 12814 %v1 = trunc <32 x i16> %v0 to <32 x i8>15 store <32 x i8> %v1, ptr %a1, align 12816 ret void17}18 19; v32i32 -> v32i820; CHECK-LABEL: f1:21; CHECK: r[[R0:[0-9]+]] = #3222; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)23; CHECK: v[[V1:[0-9]+]].b = vdeale({{.*}},v[[V0]].b)24; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])25; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]26define void @f1(ptr %a0, ptr %a1) #0 {27 %v0 = load <32 x i32>, ptr %a0, align 12828 %v1 = trunc <32 x i32> %v0 to <32 x i8>29 store <32 x i8> %v1, ptr %a1, align 12830 ret void31}32 33; v64i16 -> v64i834; CHECK-LABEL: f2:35; CHECK: r[[R0:[0-9]+]] = #6436; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)37; CHECK: v[[V1:[0-9]+]].b = vpacke({{.*}},v[[V0]].h)38; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])39; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]40define void @f2(ptr %a0, ptr %a1) #0 {41 %v0 = load <64 x i16>, ptr %a0, align 12842 %v1 = trunc <64 x i16> %v0 to <64 x i8>43 store <64 x i8> %v1, ptr %a1, align 12844 ret void45}46 47; v64i32 -> v64i848; CHECK-LABEL: f3:49; CHECK-DAG: v[[V0:[0-9]+]] = vmem(r0+#0)50; CHECK-DAG: v[[V1:[0-9]+]] = vmem(r0+#1)51; CHECK-DAG: q[[Q0:[0-3]]] = vsetq52; CHECK: v[[V2:[0-9]+]].h = vpacke(v[[V1]].w,v[[V0]].w)53; CHECK: v[[V3:[0-9]+]].b = vpacke({{.*}},v[[V2]].h)54; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V3]]55define void @f3(ptr %a0, ptr %a1) #0 {56 %v0 = load <64 x i32>, ptr %a0, align 12857 %v1 = trunc <64 x i32> %v0 to <64 x i8>58 store <64 x i8> %v1, ptr %a1, align 12859 ret void60}61 62; v16i32 -> v16i1663; CHECK-LABEL: f4:64; CHECK: r[[R0:[0-9]+]] = #3265; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)66; CHECK: v[[V1:[0-9]+]].h = vpacke({{.*}},v[[V0]].w)67; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])68; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]69define void @f4(ptr %a0, ptr %a1) #0 {70 %v0 = load <16 x i32>, ptr %a0, align 12871 %v1 = trunc <16 x i32> %v0 to <16 x i16>72 store <16 x i16> %v1, ptr %a1, align 12873 ret void74}75 76; v32i32 -> v32i1677; CHECK-LABEL: f5:78; CHECK: r[[R0:[0-9]+]] = #6479; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)80; CHECK: v[[V1:[0-9]+]].h = vpacke({{.*}},v[[V0]].w)81; CHECK: q[[Q0:[0-3]]] = vsetq(r[[R0]])82; CHECK: if (q[[Q0]]) vmem(r1+#0) = v[[V1]]83define void @f5(ptr %a0, ptr %a1) #0 {84 %v0 = load <32 x i32>, ptr %a0, align 12885 %v1 = trunc <32 x i32> %v0 to <32 x i16>86 store <32 x i16> %v1, ptr %a1, align 12887 ret void88}89 90; v8i32 -> v8i891; CHECK-LABEL: f6:92; CHECK: v[[V0:[0-9]+]] = vmem(r0+#0)93; CHECK: v[[V1:[0-9]+]].b = vdeale({{.*}},v[[V0]].b)94; CHECK: vmem(r[[R0:[0-9]+]]+#0) = v[[V1]]95; CHECK-DAG: r[[R1:[0-9]+]] = memw(r[[R0]]+#0)96; CHECK-DAG: r[[R2:[0-9]+]] = memw(r[[R0]]+#4)97; CHECK: memd(r1+#0) = r[[R2]]:[[R1]]98define void @f6(ptr %a0, ptr %a1) #0 {99 %v0 = load <8 x i32>, ptr %a0, align 128100 %v1 = trunc <8 x i32> %v0 to <8 x i8>101 store <8 x i8> %v1, ptr %a1, align 128102 ret void103}104 105 106attributes #0 = { "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length128b,-packets" }107 108