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1; RUN: llc -mtriple=hexagon -O2 < %s | FileCheck %s2;3; This checks that predicate registers are moved to GPRs instead of spilling4; where possible.5 6; CHECK: p0 =7; CHECK-NOT: memw(r298 9define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {10entry:11 %cmp = icmp eq i32 %a, 112 %cmp1 = icmp eq i32 %b, 213 %or.cond = and i1 %cmp, %cmp114 %cmp3 = icmp eq i32 %c, 315 %or.cond30 = and i1 %or.cond, %cmp316 %cmp5 = icmp eq i32 %d, 417 %or.cond31 = and i1 %or.cond30, %cmp518 %cmp7 = icmp eq i32 %e, 519 %or.cond32 = and i1 %or.cond31, %cmp720 %ret.0 = zext i1 %or.cond32 to i3221 %cmp8 = icmp eq i32 %a, 322 %cmp10 = icmp eq i32 %b, 423 %or.cond33 = and i1 %cmp8, %cmp1024 %cmp12 = icmp eq i32 %c, 525 %or.cond34 = and i1 %or.cond33, %cmp1226 %cmp14 = icmp eq i32 %d, 627 %or.cond35 = and i1 %or.cond34, %cmp1428 %cmp16 = icmp eq i32 %e, 729 %or.cond36 = and i1 %or.cond35, %cmp1630 %ret.1 = select i1 %or.cond36, i32 2, i32 %ret.031 %cmp21 = icmp eq i32 %b, 832 %or.cond37 = and i1 %cmp, %cmp2133 %cmp23 = icmp eq i32 %c, 234 %or.cond38 = and i1 %or.cond37, %cmp2335 %cmp25 = icmp eq i32 %d, 136 %or.cond39 = and i1 %or.cond38, %cmp2537 %cmp27 = icmp eq i32 %e, 338 %or.cond40 = and i1 %or.cond39, %cmp2739 %ret.2 = select i1 %or.cond40, i32 3, i32 %ret.140 ret i32 %ret.241}42 43