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1# RUN: llc -mtriple=hexagon -run-pass post-RA-sched %s -o - | FileCheck %s2# RUN: llc -mtriple=hexagon -passes=post-RA-sched %s -o - | FileCheck %s3 4# Test that the Post RA scheduler does not schedule back-to-back loads5# when there is another instruction to schedule. The scheduler avoids6# the back-to-back loads to reduce potential bank conflicts.7 8# CHECK: = L2_loadrigp9# CHECK: = A2_tfr10# CHECK: = L2_loadrigp11 12# CHECK: = S2_tstbit_i13# CHECK: = L4_loadri_rr14# CHECK: = L4_loadri_rr15 16--- |17 %s.0 = type { [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [24 x i32], [3 x i32], [24 x i32], [8 x %s.1], [5 x i32] }18 %s.1 = type { i32, i32 }19 20 @g0 = global i64 021 @g1 = global i64 022 @g2 = global i32 023 @g3 = global i32 024 @g4 = global i8 025 26 declare i32 @llvm.hexagon.S2.cl0(i32) #027 declare i32 @llvm.hexagon.S2.setbit.r(i32, i32) #028 declare i64 @llvm.hexagon.M2.vmpy2s.s0(i32, i32) #029 declare i64 @llvm.hexagon.M2.vmac2s.s0(i64, i32, i32) #030 declare i64 @llvm.hexagon.A2.vaddws(i64, i64) #031 declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #032 33 define void @f0(i32 %a0) {34 b0:35 %v0 = bitcast ptr inttoptr (i32 -121502345 to ptr) to ptr36 br label %b137 38 b1: ; preds = %b5, %b039 %v1 = phi i32 [ 0, %b0 ], [ %v28, %b5 ]40 %v2 = phi i32 [ 0, %b0 ], [ %v27, %b5 ]41 %v3 = load i32, ptr @g2, align 442 %v4 = load i32, ptr @g3, align 843 %v5 = and i32 %v4, %v344 %v6 = getelementptr [10 x %s.0], ptr %v0, i32 0, i32 %v245 %v8 = getelementptr %s.0, ptr %v6, i32 0, i32 1246 %v9 = getelementptr %s.0, ptr %v6, i32 0, i32 1347 br label %b248 49 b2: ; preds = %b4, %b150 %v10 = phi i64 [ %v24, %b4 ], [ 0, %b1 ]51 %v11 = phi i32 [ %v13, %b4 ], [ %v5, %b1 ]52 %v12 = tail call i32 @llvm.hexagon.S2.cl0(i32 %v11)53 %v13 = tail call i32 @llvm.hexagon.S2.setbit.r(i32 %v11, i32 %v12)54 %v14 = getelementptr [24 x i32], ptr %v8, i32 0, i32 %v1255 %v15 = load i32, ptr %v14, align 456 %v16 = tail call i64 @llvm.hexagon.M2.vmpy2s.s0(i32 %v15, i32 %v15)57 %v17 = getelementptr [24 x i32], ptr %v9, i32 0, i32 %v1258 %v18 = load i32, ptr %v17, align 459 %v19 = tail call i64 @llvm.hexagon.M2.vmac2s.s0(i64 %v16, i32 %v18, i32 %v18)60 %v20 = load i8, ptr @g4, align 161 %v21 = and i8 %v20, 162 %v22 = icmp eq i8 %v21, 063 br i1 %v22, label %b3, label %b464 65 b3: ; preds = %b266 %v23 = tail call i64 @llvm.hexagon.A2.vaddws(i64 %v10, i64 %v19)67 store i64 %v23, ptr @g0, align 868 br label %b469 70 b4: ; preds = %b3, %b271 %v24 = phi i64 [ %v23, %b3 ], [ %v10, %b2 ]72 %v25 = icmp eq i32 %v13, 073 br i1 %v25, label %b5, label %b274 75 b5: ; preds = %b476 %v26 = add i32 %v2, 177 %v27 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %v26, i32 10)78 %v28 = add i32 %v1, 179 %v29 = icmp eq i32 %v28, %a080 br i1 %v29, label %b6, label %b181 82 b6: ; preds = %b583 store i64 %v19, ptr @g1, align 884 ret void85 }86 87 attributes #0 = { nounwind readnone }88 89...90---91name: f092alignment: 1693tracksRegLiveness: true94registers:95liveins:96 - { reg: '$r0', virtual-reg: '' }97fixedStack:98stack:99constants:100body: |101 bb.0:102 successors: %bb.1(0x80000000)103 liveins: $r0:0x00000001104 105 $r3 = A2_tfrsi 0106 $r2 = A2_tfrsi -121502345107 $r4 = A2_tfrsi 10108 J2_loop0r %bb.1, killed $r0, implicit-def $lc0, implicit-def $sa0, implicit-def $usr109 110 bb.1 (machine-block-address-taken):111 successors: %bb.2(0x80000000)112 liveins: $lc0:0x00000004, $r2:0x00000001, $r3:0x00000001, $r4:0x00000001, $sa0:0x00000004113 114 $r5 = M2_mpysip $r3, 1824115 $r7 = L2_loadrigp @g2, implicit $gp :: (dereferenceable load (s32) from @g2)116 $r8 = L2_loadrigp @g3, implicit killed $gp :: (dereferenceable load (s32) from @g3, align 8)117 $r6 = A2_tfr $r5118 $r7 = A2_and killed $r8, killed $r7119 $r5 = M2_accii killed $r5, $r2, 1248120 $r6 = M2_accii killed $r6, $r2, 1152121 $d0 = A2_tfrpi 0122 123 bb.2:124 successors: %bb.3(0x04000000), %bb.2(0x7c000000)125 liveins: $lc0:0x00000004, $r0:0x00000001, $r1:0x00000001, $r2:0x00000001, $r3:0x00000001, $r4:0x00000001, $r5:0x00000001, $r6:0x00000001, $r7:0x00000001, $sa0:0x00000004126 127 $r8 = S2_cl0 $r7128 $r12 = L2_loadrubgp @g4, implicit $gp :: (dereferenceable load (s8) from @g4)129 $r7 = S2_setbit_r killed $r7, $r8130 $r9 = L4_loadri_rr $r6, $r8, 2 :: (load (s32) from %ir.v14)131 $r13 = L4_loadri_rr $r5, killed $r8, 2 :: (load (s32) from %ir.v17)132 $d4 = M2_vmpy2s_s0 killed $r9, $r9, implicit-def dead $usr_ovf133 $p0 = S2_tstbit_i killed $r12, 0134 $d4 = M2_vmac2s_s0 killed $d4, killed $r13, $r13, implicit-def dead $usr_ovf135 $p1 = C2_cmpeqi $r7, 0136 $d6 = A2_vaddws $d0, $d4, implicit-def dead $usr_ovf137 $d0 = A2_tfrpt $p0, killed $d0, implicit $d0138 S4_pstorerdf_abs $p0, @g0, $d6, implicit killed $gp :: (store (s64) into @g0)139 $d0 = A2_tfrpf killed $p0, killed $d6, implicit killed $d0140 J2_jumpf killed $p1, %bb.2, implicit-def dead $pc141 142 bb.3:143 successors: %bb.4(0x04000000), %bb.1(0x7c000000)144 liveins: $lc0:0x00000004, $r2:0x00000001, $r3:0x00000001, $r4:0x00000001, $r8:0x00000001, $r9:0x00000001, $sa0:0x00000004145 146 $r3 = A2_addi killed $r3, 1147 $r3 = A4_modwrapu killed $r3, $r4148 ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0149 150 bb.4:151 liveins: $r8:0x00000001, $r9:0x00000001152 153 S2_storerdgp @g1, killed $d4, implicit killed $gp :: (store (s64) into @g1)154 PS_jmpret killed $r31, implicit-def dead $pc155...156 157