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1; RUN: llc -mtriple=hexagon < %s2; REQUIRES: asserts3 4; Test that the accessSize is set on a post-increment store. If not, an assert5; is triggered in getBaseAndOffset()6 7%struct.A = type { i8, i32, i32, i32, [10 x i32], [10 x i32], [80 x i32], [80 x i32], [8 x i32], i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 }8 9; Function Attrs: nounwind10define fastcc void @Decoder_amr(i8 zeroext %mode) #0 {11entry:12 br label %for.cond64.preheader.i13 14for.cond64.preheader.i:15 %i.1984.i = phi i32 [ 0, %entry ], [ %inc166.i.1, %for.cond64.preheader.i ]16 %inc166.i = add nsw i32 %i.1984.i, 117 %arrayidx71.i1422.1 = getelementptr inbounds %struct.A, ptr undef, i32 0, i32 7, i32 %inc166.i18 %storemerge800.i.1 = select i1 undef, i32 1310, i32 undef19 %sub156.i.1 = sub nsw i32 0, %storemerge800.i.120 %sub156.storemerge800.i.1 = select i1 undef, i32 %storemerge800.i.1, i32 %sub156.i.121 store i32 %sub156.storemerge800.i.1, ptr %arrayidx71.i1422.1, align 422 store i32 0, ptr undef, align 423 %inc166.i.1 = add nsw i32 %i.1984.i, 224 br label %for.cond64.preheader.i25 26if.end:27 ret void28}29 30attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }31