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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=hexagon --mattr=+hvx-length128b,+hvx-qfloat,+hvxv81,+v81 < %s | FileCheck %s3 4; Function Attrs: mustprogress nounwind5 6define dso_local void @bf16_vec_add(ptr noundef %c, ptr noundef %a, ptr noundef %b) local_unnamed_addr #0 {7; CHECK-LABEL: bf16_vec_add:8; CHECK: // %bb.0: // %entry9; CHECK-NEXT: {10; CHECK-NEXT: [[R7:r[0-9]+]] = #-411; CHECK-NEXT: [[V0:v[0-9]+]] = vmemu([[R2:r[0-9]+]]+#0)12; CHECK-NEXT: }13; CHECK-NEXT: {14; CHECK-NEXT: [[R2]] = ##3276815; CHECK-NEXT: [[V1:v[0-9]+]] = vmemu([[R1:r[0-9]+]]+#0)16; CHECK-NEXT: }17; CHECK-NEXT: {18; CHECK-NEXT: [[R6:r[0-9]+]] = ##13107119; CHECK-NEXT: [[V2:v[0-9]+]] = vxor([[V0]],[[V0]])20; CHECK-NEXT: [[V3:v[0-9]+]] = vxor([[V1]],[[V1]])21; CHECK-NEXT: }22; CHECK-NEXT: {23; CHECK-NEXT: [[V25:v[0-9]+]] = vsplat([[R2]])24; CHECK-NEXT: [[R5:r[0-9]+]] = #1625; CHECK-NEXT: [[V5_4:v[0-9]+:[0-9]+]].h = vshuffoe([[V0]].h,[[V2]].h)26; CHECK-NEXT: }27; CHECK-NEXT: {28; CHECK-NEXT: [[V26:v[0-9]+]] = vsplat([[R6]])29; CHECK-NEXT: [[R4:r[0-9]+]] = #3276730; CHECK-NEXT: [[V31_30:v[0-9]+:[0-9]+]].h = vshuffoe([[V1]].h,[[V3]].h)31; CHECK-NEXT: }32; CHECK-NEXT: {33; CHECK-NEXT: [[V5_4]] = vshuff([[V5:v[0-9]+]],[[V4:v[0-9]+]],[[R7]])34; CHECK-NEXT: }35; CHECK-NEXT: {36; CHECK-NEXT: [[V31:v[0-9]+]].h = vsplat([[R4]])37; CHECK-NEXT: [[V3_2:v[0-9]+:[0-9]+]] = vshuff([[V31]],[[V30:v[0-9]+]],[[R7]])38; CHECK-NEXT: }39; CHECK-NEXT: {40; CHECK-NEXT: [[V2]].qf32 = vadd([[V2]].sf,[[V4]].sf)41; CHECK-NEXT: }42; CHECK-NEXT: {43; CHECK-NEXT: [[V3]].qf32 = vadd([[V3]].sf,[[V5]].sf)44; CHECK-NEXT: }45; CHECK-NEXT: {46; CHECK-NEXT: [[V2]].sf = [[V2]].qf3247; CHECK-NEXT: }48; CHECK-NEXT: {49; CHECK-NEXT: [[V3]].sf = [[V3]].qf3250; CHECK-NEXT: [[V27:v[0-9]+]] = vand([[V2]],[[V25]])51; CHECK-NEXT: [[V28:v[0-9]+]] = vand([[V2]],[[V26]])52; CHECK-NEXT: [[Q2:q[0-9]+]] = vcmp.eq([[V2]].sf,[[V2]].sf)53; CHECK-NEXT: }54; CHECK-NEXT: {55; CHECK-NEXT: [[V29:v[0-9]+]] = vand([[V3]],[[V25]])56; CHECK-NEXT: [[V1]] = vand([[V3]],[[V26]])57; CHECK-NEXT: [[Q0:q[0-9]+]] = vcmp.eq([[V28]].w,[[V25]].w)58; CHECK-NEXT: [[V4]].w = vadd([[V2]].w,[[V27]].w)59; CHECK-NEXT: }60; CHECK-NEXT: {61; CHECK-NEXT: [[V5]].w = vadd([[V3]].w,[[V29]].w)62; CHECK-NEXT: [[Q1:q[0-9]+]] = vcmp.eq([[V1]].w,[[V25]].w)63; CHECK-NEXT: [[V30:v[0-9]+]] = vmux([[Q0]],[[V2]],[[V4]])64; CHECK-NEXT: [[Q3:q[0-9]+]] = vcmp.eq([[V3]].sf,[[V3]].sf)65; CHECK-NEXT: }66; CHECK-NEXT: {67; CHECK-NEXT: [[V1]] = vmux([[Q1]],[[V3]],[[V5]])68; CHECK-NEXT: }69; CHECK-NEXT: {70; CHECK-NEXT: [[V0]].uw = vlsr([[V30]].uw,[[R5]])71; CHECK-NEXT: }72; CHECK-NEXT: {73; CHECK-NEXT: [[V1]].uw = vlsr([[V1]].uw,[[R5]])74; CHECK-NEXT: [[V0]] = vmux([[Q2]],[[V0]],[[V31]])75; CHECK-NEXT: }76; CHECK-NEXT: {77; CHECK-NEXT: [[V1]] = vmux([[Q3]],[[V1]],[[V31]])78; CHECK-NEXT: }79; CHECK-NEXT: {80; CHECK-NEXT: [[V0]].uh = vpack([[V1]].w,[[V0]].w):sat81; CHECK-NEXT: }82; CHECK-NEXT: {83; CHECK-NEXT: jumpr [[R31:r[0-9]+]]84; CHECK-NEXT: vmemu([[R0:r[0-9]+]]+#0) = [[V0]]85; CHECK-NEXT: }86 87 88entry:89 %0 = load <64 x bfloat>, ptr %a, align 290 %1 = load <64 x bfloat>, ptr %b, align 291 %add.ripple.vectorized = fadd <64 x bfloat> %0, %192 store <64 x bfloat> %add.ripple.vectorized, ptr %c, align 293 ret void94}95 96define dso_local void @copy1d(ptr noundef readonly captures(none) %X, ptr noundef writeonly captures(none) %Y) local_unnamed_addr #0 {97; CHECK-LABEL: copy1d:98; CHECK: // %bb.0: // %entry99; CHECK-NEXT: {100; CHECK-NEXT: v0 = vmemu(r0+#1)101; CHECK-NEXT: }102; CHECK-NEXT: {103; CHECK-NEXT: v1 = vmemu(r0+#0)104; CHECK-NEXT: }105; CHECK-NEXT: {106; CHECK-NEXT: vmemu(r1+#1) = v0107; CHECK-NEXT: }108; CHECK-NEXT: {109; CHECK-NEXT: jumpr r31110; CHECK-NEXT: vmemu(r1+#0) = v1111; CHECK-NEXT: }112entry:113 %0 = load <128 x half>, ptr %X, align 2114 store <128 x half> %0, ptr %Y, align 2115 ret void116}117