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1; RUN: llc -mtriple=hexagon -hexagon-initial-cfg-cleanup=0 -hexagon-instsimplify=0 < %s | FileCheck %s2 3; Check for successful compilation.4; CHECK: r{{[0-9]+}} = insert(r{{[0-9]+}},#1,#31)5 6; This cannot be a .mir test, because the failure depends on ordering of7; virtual registers, and the .mir loader renumbers them in a way that hides8; the problem.9 10target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"11target triple = "hexagon"12 13; Function Attrs: nounwind14define void @f0() #0 align 2 {15b0:16 br label %b117 18b1: ; preds = %b3, %b019 %v0 = phi i64 [ 0, %b0 ], [ %v6, %b3 ]20 br i1 undef, label %b2, label %b321 22b2: ; preds = %b123 br label %b324 25b3: ; preds = %b2, %b126 %v1 = phi i64 [ undef, %b2 ], [ %v0, %b1 ]27 %v2 = and i64 %v1, 128 %v3 = trunc i64 %v2 to i3229 %v4 = tail call i32 @llvm.hexagon.C2.mux(i32 %v3, i32 undef, i32 undef)30 %v5 = trunc i32 %v4 to i831 store i8 %v5, ptr undef, align 132 %v6 = lshr i64 %v1, 133 br label %b134}35 36; Function Attrs: nounwind readnone37declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) #138 39attributes #0 = { nounwind "target-cpu"="hexagonv60" }40attributes #1 = { nounwind readnone }41