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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3target triple = "hexagon"4 5; CHECK-LABEL: xh_sh6; CHECK: sath7; CHECK-NOT: sxth8define i32 @xh_sh(i32 %x) local_unnamed_addr #0 {9entry:10 %0 = tail call i32 @llvm.hexagon.A2.sath(i32 %x)11 %1 = tail call i32 @llvm.hexagon.A2.sxth(i32 %0)12 ret i32 %113}14 15; CHECK-LABEL: xb_sb16; CHECK: satb17; CHECK-NOT: sxtb18define i32 @xb_sb(i32 %x) local_unnamed_addr #0 {19entry:20 %0 = tail call i32 @llvm.hexagon.A2.satb(i32 %x)21 %1 = tail call i32 @llvm.hexagon.A2.sxtb(i32 %0)22 ret i32 %123}24 25; CHECK-LABEL: xuh_suh26; CHECK: satuh27; CHECK-NOT: zxth28define i32 @xuh_suh(i32 %x) local_unnamed_addr #0 {29entry:30 %0 = tail call i32 @llvm.hexagon.A2.satuh(i32 %x)31 %1 = tail call i32 @llvm.hexagon.A2.zxth(i32 %0)32 ret i32 %133}34 35; CHECK-LABEL: xub_sub36; CHECK: satub37; CHECK-NOT: zxtb38define i32 @xub_sub(i32 %x) local_unnamed_addr #0 {39entry:40 %0 = tail call i32 @llvm.hexagon.A2.satub(i32 %x)41 %1 = tail call i32 @llvm.hexagon.A2.zxtb(i32 %0)42 ret i32 %143}44 45 46declare i32 @llvm.hexagon.A2.sxtb(i32) #147declare i32 @llvm.hexagon.A2.sxth(i32) #148declare i32 @llvm.hexagon.A2.zxtb(i32) #149declare i32 @llvm.hexagon.A2.zxth(i32) #150 51declare i32 @llvm.hexagon.A2.satb(i32) #152declare i32 @llvm.hexagon.A2.sath(i32) #153declare i32 @llvm.hexagon.A2.satub(i32) #154declare i32 @llvm.hexagon.A2.satuh(i32) #155 56attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }57attributes #1 = { nounwind readnone }58