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1; RUN: llc -mtriple=hexagon -hexbit-extract=0 < %s | FileCheck %s2 3; Make sure we don't generate zxtb to transfer a predicate register into4; a general purpose register.5 6; CHECK: r0 = p07; CHECK-NOT: zxtb(p8; CHECK-NOT: and(p9; CHECK-NOT: extract(p10; CHECK-NOT: extractu(p11 12target triple = "hexagon"13 14; Function Attrs: nounwind15define i32 @fred() local_unnamed_addr #0 {16entry:17 %0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef)18 ret i32 %019}20 21declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #122 23attributes #0 = { nounwind "target-cpu"="hexagonv5" }24attributes #1 = { nounwind readnone }25