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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2 3; This testcase would fail on a bitcast from v64i16 to v32i32. Check that4; is compiles without errors.5; CHECK: valign6; CHECK: vshuff7 8target triple = "hexagon"9 10declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #011declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #012declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #013 14define void @fred(ptr %a0, ptr %a1) #1 {15entry:16 %t0 = bitcast <64 x i16> zeroinitializer to <32 x i32>17 %t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2)18 %t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -2)19 %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2)20 store <64 x i16> zeroinitializer, ptr %a0, align 12821 store <32 x i32> %t3, ptr %a1, align 12822 ret void23}24 25 26attributes #0 = { nounwind readnone }27attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }28