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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s3; Testing bitreverse load intrinsics:4; Q6_bitrev_load_update_D(inputLR, pDelay, nConvLength);5; Q6_bitrev_load_update_W(inputLR, pDelay, nConvLength);6; Q6_bitrev_load_update_H(inputLR, pDelay, nConvLength);7; Q6_bitrev_load_update_UH(inputLR, pDelay, nConvLength);8; Q6_bitrev_load_update_UB(inputLR, pDelay, nConvLength);9; Q6_bitrev_load_update_B(inputLR, pDelay, nConvLength);10; producing these instructions:11; r3:2 = memd(r0++m0:brev)12; r1 = memw(r0++m0:brev)13; r1 = memh(r0++m0:brev)14; r1 = memuh(r0++m0:brev)15; r1 = memub(r0++m0:brev)16; r1 = memb(r0++m0:brev)17 18target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"19target triple = "hexagon-unknown--elf"20 21; CHECK: @call_brev_ldd22define ptr @call_brev_ldd(ptr %ptr, i64 %dst, i32 %mod) local_unnamed_addr #0 {23entry:24; CHECK: = memd(r{{[0-9]*}}++m{{[0-1]}}:brev)25 %0 = tail call { i64, ptr } @llvm.hexagon.L2.loadrd.pbr(ptr %ptr, i32 %mod)26 %1 = extractvalue { i64, ptr } %0, 127 ret ptr %128}29 30; CHECK: @call_brev_ldw31define ptr @call_brev_ldw(ptr %ptr, i32 %dst, i32 %mod) local_unnamed_addr #0 {32entry:33; CHECK: = memw(r{{[0-9]*}}++m{{[0-1]}}:brev)34 %0 = tail call { i32, ptr } @llvm.hexagon.L2.loadri.pbr(ptr %ptr, i32 %mod)35 %1 = extractvalue { i32, ptr } %0, 136 ret ptr %137}38 39; CHECK: @call_brev_ldh40define ptr @call_brev_ldh(ptr %ptr, i16 signext %dst, i32 %mod) local_unnamed_addr #0 {41entry:42; CHECK: = memh(r{{[0-9]*}}++m{{[0-1]}}:brev)43 %0 = tail call { i32, ptr } @llvm.hexagon.L2.loadrh.pbr(ptr %ptr, i32 %mod)44 %1 = extractvalue { i32, ptr } %0, 145 ret ptr %146}47 48; CHECK: @call_brev_lduh49define ptr @call_brev_lduh(ptr %ptr, i16 zeroext %dst, i32 %mod) local_unnamed_addr #0 {50entry:51; CHECK: = memuh(r{{[0-9]*}}++m{{[0-1]}}:brev)52 %0 = tail call { i32, ptr } @llvm.hexagon.L2.loadruh.pbr(ptr %ptr, i32 %mod)53 %1 = extractvalue { i32, ptr } %0, 154 ret ptr %155}56 57; CHECK: @call_brev_ldb58define ptr @call_brev_ldb(ptr %ptr, i8 signext %dst, i32 %mod) local_unnamed_addr #0 {59entry:60; CHECK: = memb(r{{[0-9]*}}++m{{[0-1]}}:brev)61 %0 = tail call { i32, ptr } @llvm.hexagon.L2.loadrb.pbr(ptr %ptr, i32 %mod)62 %1 = extractvalue { i32, ptr } %0, 163 ret ptr %164}65 66; Function Attrs: nounwind readonly67; CHECK: @call_brev_ldub68define ptr @call_brev_ldub(ptr %ptr, i8 zeroext %dst, i32 %mod) local_unnamed_addr #0 {69entry:70; CHECK: = memub(r{{[0-9]*}}++m{{[0-1]}}:brev)71 %0 = tail call { i32, ptr } @llvm.hexagon.L2.loadrub.pbr(ptr %ptr, i32 %mod)72 %1 = extractvalue { i32, ptr } %0, 173 ret ptr %174}75 76declare { i64, ptr } @llvm.hexagon.L2.loadrd.pbr(ptr, i32) #177declare { i32, ptr } @llvm.hexagon.L2.loadri.pbr(ptr, i32) #178declare { i32, ptr } @llvm.hexagon.L2.loadrh.pbr(ptr, i32) #179declare { i32, ptr } @llvm.hexagon.L2.loadruh.pbr(ptr, i32) #180declare { i32, ptr } @llvm.hexagon.L2.loadrb.pbr(ptr, i32) #181declare { i32, ptr } @llvm.hexagon.L2.loadrub.pbr(ptr, i32) #182 83attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" }84attributes #1 = { nounwind readonly }85