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1; RUN: llc -mtriple=hexagon < %s | FileCheck %s2; RUN: llc -mtriple=hexagon -verify-machineinstrs=true < %s | FileCheck %s3; Test these 5 bitreverse store intrinsics:4; Q6_bitrev_store_update_D(inputLR, pDelay, nConvLength);5; Q6_bitrev_store_update_W(inputLR, pDelay, nConvLength);6; Q6_bitrev_store_update_HL(inputLR, pDelay, nConvLength);7; Q6_bitrev_store_update_HH(inputLR, pDelay, nConvLength);8; Q6_bitrev_store_update_B(inputLR, pDelay, nConvLength);9; producing these instructions:10; memd(r0++m0:brev) = r1:011; memw(r0++m0:brev) = r012; memh(r0++m0:brev) = r313; memh(r0++m0:brev) = r3.h14; memb(r0++m0:brev) = r315 16; ModuleID = 'brev_st.i'17target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32"18target triple = "hexagon"19 20define i64 @foo(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {21entry:22 %conv = zext i16 %filtMemLen to i3223 %shr2 = lshr i32 %conv, 124 %idxprom = sext i16 %filtMemIndex to i3225 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom26 %sub = sub i32 13, %shr227 %shl = shl i32 1, %sub28; CHECK: memd(r{{[0-9]*}}++m{{[0-1]}}:brev)29 %0 = tail call ptr @llvm.hexagon.S2.storerd.pbr(ptr %arrayidx, i64 undef, i32 %shl)30 ret i64 031}32 33declare ptr @llvm.hexagon.S2.storerd.pbr(ptr, i64, i32) nounwind34 35define i32 @foo1(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {36entry:37 %conv = zext i16 %filtMemLen to i3238 %shr1 = lshr i32 %conv, 139 %idxprom = sext i16 %filtMemIndex to i3240 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom41 %sub = sub i32 14, %shr142 %shl = shl i32 1, %sub43; CHECK: memw(r{{[0-9]*}}++m{{[0-1]}}:brev)44 %0 = tail call ptr @llvm.hexagon.S2.storeri.pbr(ptr %arrayidx, i32 undef, i32 %shl)45 ret i32 046}47 48declare ptr @llvm.hexagon.S2.storeri.pbr(ptr, i32, i32) nounwind49 50define signext i16 @foo2(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {51entry:52 %conv = zext i16 %filtMemLen to i3253 %shr2 = lshr i32 %conv, 154 %idxprom = sext i16 %filtMemIndex to i3255 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom56 %sub = sub i32 15, %shr257 %shl = shl i32 1, %sub58; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev)59 %0 = tail call ptr @llvm.hexagon.S2.storerh.pbr(ptr %arrayidx, i32 0, i32 %shl)60 ret i16 061}62 63declare ptr @llvm.hexagon.S2.storerh.pbr(ptr, i32, i32) nounwind64 65define signext i16 @foo3(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {66entry:67 %conv = zext i16 %filtMemLen to i3268 %shr2 = lshr i32 %conv, 169 %idxprom = sext i16 %filtMemIndex to i3270 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom71 %sub = sub i32 15, %shr272 %shl = shl i32 1, %sub73; CHECK: memh(r{{[0-9]*}}++m{{[0-1]}}:brev) = r{{[0-9]*}}.h74 %0 = tail call ptr @llvm.hexagon.S2.storerf.pbr(ptr %arrayidx, i32 0, i32 %shl)75 ret i16 076}77 78declare ptr @llvm.hexagon.S2.storerf.pbr(ptr, i32, i32) nounwind79 80define zeroext i8 @foo5(i16 zeroext %filtMemLen, ptr %filtMemLR, i16 signext %filtMemIndex) nounwind {81entry:82 %conv = zext i16 %filtMemLen to i3283 %shr2 = lshr i32 %conv, 184 %idxprom = sext i16 %filtMemIndex to i3285 %arrayidx = getelementptr inbounds i16, ptr %filtMemLR, i32 %idxprom86 %sub = sub nsw i32 16, %shr287 ; CHECK: memb(r{{[0-9]*}}++m{{[0-1]}}:brev)88 %shl = shl i32 1, %sub89 %0 = tail call ptr @llvm.hexagon.S2.storerb.pbr(ptr %arrayidx, i32 0, i32 %shl)90 ret i8 091}92 93declare ptr @llvm.hexagon.S2.storerb.pbr(ptr, i32, i32) nounwind94 95!0 = !{!"omnipotent char", !1}96!1 = !{!"Simple C/C++ TBAA"}97!2 = !{!"int", !0}98!3 = !{!"short", !0}99